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Aaeon VPC-5500S User Manual

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VPC-5500S
Mobile NVR
th
User's Manual 6
Ed
Last Updated: November 4, 2016

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  • Page 1 VPC-5500S Mobile NVR User’s Manual 6 Last Updated: November 4, 2016...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp.  Intel, Pentium, Celeron, and Xeon are registered trademarks of Intel Corporation  Core, Atom are trademarks of Intel Corporation ...
  • Page 4 Before setting up your product, please make sure the following items have been shipped: Item Quantity VPC-5500S  Product DVD with User’s Manual (in pdf) and drivers  If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the AAEON.com for the latest version of this document. Preface...
  • Page 6 All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale. Do not use any cables or adapters not supplied by AAEON to prevent system malfunction or fires.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON Embedded Box PC/ Industrial System 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) 印刷电路板 ○ ○ ○ ○ ○ ○ 及其电子组件 外部信号 ○ ○ ○ ○ ○ ○...
  • Page 10 China RoHS Requirement (EN) Poisonous or Hazardous Substances or Elements in Products AAEON Embedded Box PC/ Industrial System Poisonous or Hazardous Substances or Elements Hexavalent Polybrominated Polybrominated Component Lead Mercury Cadmium Chromium Biphenyls Diphenyl Ethers (Pb) (Hg) (Cd) (Cr(VI)) (PBB) (PBDE) PCB &...

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications ..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................5 Dimensions ....................... 6 Jumpers and Connectors ..................10 List of Jumpers ....................... 12 2.3.1 Clear CMOS Selection (CN11/CN13) ..........13 2.3.2 Auto Power Button Selection (CN23) ..........
  • Page 12 3.4.4 Advanced: SATA Configuration ............31 3.4.5 Advanced: USB Configuration ............32 3.4.6 Advanced: F81666 Super IO Configuration ........33 3.4.6.1 F81666 Super IO Configuration: Serial Port 1 Configuration ....................34 3.4.6.2 F81666 Super IO Configuration: Serial Port 2 Configuration ....................35 3.4.6.3 F81666 Super IO Configuration: Serial Port 3 Configuration ....................
  • Page 13 Product CD/DVD ....................56 Appendix A - Watchdog Timer Programming ..............65 Watchdog Timer Initial Program ................ 66 Appendix B - I/O Information ....................71 I/O Address Map ....................72 Memory Address Map ..................74 IRQ Mapping Chart ....................76 DMA Channel Assignments ................

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications  CPU Intel Core™ i7-4700EQ, up to 3.4 GHz ® Intel Core™ i5-4400E, up to 3.3 GHz ® Intel ® Core™ i3-4100EQ, 2.4 GHz  Chipset QM87  System Memory DDR3L 1333/1600 SODIMM x 2, up to. 16 GB ...
  • Page 16 3-pin terminal block for remote power support x 1 DI/O x 1 CAN Bus x 1 (read only) Expansion MiniCard Full MiniCard x 3 (2 for USB only, 1 full  function) Indicator Power LED (Red) x 1  HDD LED (Green) x 1 WLAN LED (Red, for mPCIe) x 3 Power Requirement Vehicle power:...
  • Page 17 Windows ® Windows ® Embedded Standard 7 Windows ® Embedded Standard 8 Linux by Fedora Chapter 1 – Product Specifications...

  • Page 18: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 19: Dimensions

    Dimensions Chassis Chapter 2 – Hardware Information...
  • Page 20 Chapter 2 – Hardware Information...
  • Page 21 Board 195.49 192.22 188.81 186.94 187.57 172.3 181.35 170.01 179.86 145.61 148.46 142.85 142.45 118.25 107.09 103.33 102.93 78.73 70.93 69.8 64.22 63.1 56.4 49.7 46.73 44.36 38.53 16.65 32.3 12.87 26.62 26.59 12.3 17.5 11.99 11.37 11.21 Chapter 2 – Hardware Information...
  • Page 22 155.01 151.2 86.93 77.54 Note: Height of the cooler may vary depending on the customer’s setup Chapter 2 – Hardware Information...

  • Page 23: Jumpers And Connectors

    Jumpers and Connectors CN10 CN11 CN13 CN14 CN15 CN16 SLOT3 CN18 CN19 LPC1 SLOT2 CN22 DIMM1 CN24 SLOT1 CN26 CN29 CN38 CN27 CN42 SATA1 SATA2 CN30 CN32 SATA4 SATA3 CN23 CN33 Chapter 2 – Hardware Information...
  • Page 24 CN20 MSATA1 Chapter 2 – Hardware Information...

  • Page 25: List Of Jumpers

    List of Jumpers Please refer to the table below for all of the board’s jumpers that you can configure for your application Label Function CN11 Clear CMOS CN13 RTC TEST CN10 Front Plane CN23 AT/ATX CN33 COM3 RI Select Chapter 2 – Hardware Information...

  • Page 26: Clear Cmos Selection (Cn11/Cn13)

    2.3.1 Clear CMOS Selection (CN11/CN13) Function Pin (CN11/CN13) 1-2 / 1-2 Default 2-3 / 2-3 Clear CMOS 2.3.2 Auto Power Button Selection (CN23) Function Default (ATX for Box PC) Auto PWRBTN (AT for Box PC) 2.3.3 RI# Selection (CN33) Function RI (Default) 12 V Chapter 2 –...

  • Page 27: List Of Connectors

    List of Connectors Please refer to the table below for all of the board’s connectors that you can configure for your application Label Function Power Button CN10 Front Plane SIM Card(With SLOT3) SIM Card(With SLOT2) LAN2(With POE Function) LAN3(With POE Function) LAN4(With POE Function) LAN5(With POE Function) USB3.0 Con...
  • Page 28 Small 4P Power CN22.24.26.27 SATA3 Con SATA1.2.3.4 DIMM1.2 DDR3L SODIMM Power on/off delay select AUDIO1 AUDIO Con (Front + MIC) CN36 USB2.0 Con CN39 CAN Bus Con Display Port VGA1 CRT Port HDMI1 HDMI CN23 AT/ATX CN33 COM3 RI Select COM1 COM3+COM4 COM2...

  • Page 29: Front Plane Connector (Cn10)

    2.4.1 Front Plane Connector (CN10) Signal Signal PWR_SW# FPANSWH# HWRST# FPANSWH# 2.4.2 Power Input & Remote Button (CN34) Signal Signal GND_PRI PWR_IN REMOTE_SW PS_ON# 2.4.3 Digital I/O (CN35) Signal Signal +GP_V GPI0 GPO0 Chapter 2 – Hardware Information...

  • Page 30: Can Bus Connector (Cn39)

    GPI1 GPO1 GPI2 GPO2 GPI3 GPO3 2.4.4 CAN Bus Connector (CN39) Signal Signal CANH CANL Mating Connector: DINKLE EC381V-02P 2.4.5 COM3 + COM4 (COM1) (RS232 / RS485 / RS422) Signal Signal DCD(RS485 RXD(RS422 RX-) Data+/RS422 TX+) TXD(RS485 DTR(RS422 RX+) Data-/RS422 TX-) 2.4.6 COM1 + COM2 (COM2) Chapter 2 –...
  • Page 31 Signal Signal Chapter 2 – Hardware Information...

  • Page 32: Switch Pin Table

    Switch Pin Table Power on Delay Power off Delay SWITCH Pin Number 1800 Control Table Null 2Day Null Null Null Null Null Null Chapter 2 – Hardware Information...

  • Page 33: Hdd Installation

    2.5” HDD Installation Remove the top cover Loosen the screw on the HDD cover to remove it. Chapter 2 – Hardware Information...
  • Page 34 Attach the cushions to the HDD. Place the HDD onto the tray and connect the SATA and power cable Chapter 2 – Hardware Information...
  • Page 35 Cover up the tray and make sure the flutes of the cover rests on the cushions Chapter 2 – Hardware Information...

  • Page 36: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 37: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization. If an error, fatal or non-fatal, is encountered, a few short beeps or an error message will be outputted. The board can usually continue the boot up sequence with non-fatal errors. The system configuration verification routines check the current system configuration against the values stored in the CMOS memory.

  • Page 38: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 39: Setup Submenu: Main

    Setup submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 40: Setup Submenu: Advanced

    Setup submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 41: Advanced: Cpu Configuration

    3.4.1 Advanced: CPU Configuration Chapter 3 – AMI BIOS Setup...

  • Page 42: Advanced: Amt Configuration

    3.4.2 Advanced: AMT Configuration Options summary: Enable Optimal Default, Failsafe Default Intel AMT Disable Enable/Disable Intel (R) Active Management Technology BIOS Extension. Note : iAMT H/W is always enabled. This option just controls the BIOS extension execution. If enabled, this requires additional firmware in the SPI device Disable Optimal Default, Failsafe Default...

  • Page 43: Advanced: Trusted Computing

    3.4.3 Advanced: Trusted Computing Options summary: Enable Security Device Support Disable Optimal Default, Failsafe Default Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. Chapter 3 – AMI BIOS Setup...

  • Page 44: Advanced: Sata Configuration

    3.4.4 Advanced: SATA Configuration Options summary: Enable Optimal Default, Failsafe Default SATA Controller(s) Disable Enable or disable SATA Device. Optimal Default, Failsafe Default SATA Mode Selection AHCI Determines how SATA controller(s) operate. Chapter 3 – AMI BIOS Setup...

  • Page 45: Advanced: Usb Configuration

    3.4.5 Advanced: USB Configuration Options summary: Enable Optimal Default, Failsafe Default Legacy USB Support Disable Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB devices available only for EFI applications.

  • Page 46: Advanced: F81666 Super Io Configuration

    3.4.6 Advanced: F81666 Super IO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 47: F81666 Super Io Configuration: Serial Port

    3.4.6.1 F81666 Super IO Configuration: Serial Port 1 Configuration Options summary: Disable Serial Port Enable Optimal Default, Failsafe Default Enable or Disable Serial Port(COM) Auto Optimal Default, Failsafe Default IO=3F8h; IRQ=4; IO=3F8h; IRQ=3,4,5,6,7,10,11,12; Change Settings IO=2F8h; IRQ=3,4,5,6,7,10,11,12; IO=3E8h; IRQ=10; IO=2E8h; IRQ=10; Select an optimal setting for Super I/O device.

  • Page 48: Configuration

    3.4.6.2 F81666 Super IO Configuration: Serial Port 2 Configuration Options summary: Disable Serial Port Enable Optimal Default, Failsafe Default Enable or Disable Serial Port(COM) Auto Optimal Default, Failsafe Default IO=2F8h; IRQ=3; IO=3F8h; IRQ=3,4; Change Settings IO=2F8h; IRQ=3,4; IO=3E8h; IRQ=3,4; IO=2E8h; IRQ=3,4; Select an optimal setting for Super I/O device.

  • Page 49: Configuration

    3.4.6.3 F81666 Super IO Configuration: Serial Port 3 Configuration Options summary: Disable Serial Port Enable Optimal Default, Failsafe Default Enable or Disable Serial Port(COM) Auto Optimal Default, Failsafe Default IO=3E8h; IRQ=10; IO=3E8h; IRQ=10; Change Settings IO=2E8h; IRQ=10; IO=2D0h; IRQ=10; IO=2C0h; IRQ=10; Select an optimal setting for Super I/O device.

  • Page 50: Configuration

    3.4.6.4 F81666 Super IO Configuration: Serial Port 4 Configuration Options summary: Disable Serial Port Enable Optimal Default, Failsafe Default Enable or Disable Serial Port(COM) Auto Optimal Default, Failsafe Default IO=2E8h; IRQ=10; IO=3E8h; IRQ=10; Change Settings IO=2E8h; IRQ=10; IO=2D0h; IRQ=10; IO=2C0h; IRQ=10; Select an optimal setting for Super I/O device.

  • Page 51: Configuration

    3.4.6.5 F81666 Super IO Configuration: Serial Port 5 Configuration default setting Options summary: ( Disable Serial Port Enable Optimal Default, Failsafe Default Enable or Disable Serial Port(COM) Auto Optimal Default, Failsafe Default IO=2F0h; IRQ=10; IO=3E8h; IRQ=10; Change Settings IO=2E8h; IRQ=10; IO=2D0h;...

  • Page 52: Configuration

    3.4.6.6 F81666 Super IO Configuration: Serial Port 6 Configuration Options summary: Disable Serial Port Enable Optimal Default, Failsafe Default Enable or Disable Serial Port(COM) Auto Optimal Default, Failsafe Default IO=2F0h; IRQ=10; IO=3E8h; IRQ=10; Change Settings IO=2E8h; IRQ=10; IO=2D0h; IRQ=10; IO=2C0h; IRQ=10; Serial Port Mode selection.

  • Page 53: Advanced: H/W Monitor

    3.4.7 Advanced: H/W Monitor Options summary: Disable Smart Fan Function Enable Optimal Default, Failsafe Default Enable or Disable Smart Fan Chapter 3 – AMI BIOS Setup...

  • Page 54: H/W Monitor: Smart Fan Mode Configuration

    3.4.7.1 H/W Monitor: Smart Fan Mode Configuration Options summary: Manual RPM Mode Manual Duty Mode Smart Fan Mode Auto RPM Mode Configuration Auto Duty-Cycle Mode Optimal Default, Failsafe Default Smart Fan Mode Select Chapter 3 – AMI BIOS Setup...

  • Page 55: Advanced: Power Management

    3.4.8 Advanced: Power Management Options summary: ATX Type Optimal Default, Failsafe Default Power Mode AT Type Select Power Supply Mode. Power off Power on Restore AC Power Loss Last State Optimal Default, Failsafe Default Select AC power state when power is re-applied after a power failure. Enable Optimal Default, Failsafe Default Wake on LAN...
  • Page 56 Enable or disable integrated LAN to wake the system. (The Wake On LAN cannot be disabled if ME is on at Sx state.) Enable Optimal Default, Failsafe Default Resume on PCIE Disable Enable/Disable Resume from PCIE signal Enable Optimal Default, Failsafe Default Resume on Ring Disable Enable/Disable Resume from RI# signal...

  • Page 57: Advanced: Dynamic Digital Io Configuration

    3.4.9 Advanced: Dynamic Digital IO Configuration Options summary: Input Optimal Default, Failsafe Default DIO[0:3] Output DIO[3:7][Output] Output Level Optimal Default, Failsafe Default Set Digital IO Output as Hi or Low Chapter 3 – AMI BIOS Setup...

  • Page 58: Advanced: Serial Port Console Redirection

    3.4.10 Advanced: Serial Port Console Redirection Options summary: Disabled Optimal Default, Failsafe Default Console Redirection Enabled Console Redirection Enable or Disable Chapter 3 – AMI BIOS Setup...

  • Page 59: Setup Submenu: Chipset

    Setup submenu: Chipset Options summary: Touch Device Enabled Optimal Default, Failsafe Default Disabled Chapter 3 – AMI BIOS Setup...

  • Page 60: Chipset: Rch-Io Configuration

    3.5.1 Chipset: RCH-IO Configuration Options summary: Auto Optimal Default, Failsafe Default Gen1 MiniCard (SLOT1) Gen1 Select PCI Express port speed Enable Optimal Default, Failsafe Default PCH LAN Controller Disable Enable or disable onboard NIC. Disable Optimal Default, Failsafe Default Enable Azalia Auto Control Detection of the Azalia device.

  • Page 61: Chipset: Rch-Io Configuration

    3.5.2 Chipset: RCH-IO Configuration Options summary Disabled VT-d Enabled Optimal Default, Failsafe Default Check to enable VT-d function on MCH. Auto Optimal Default, Failsafe Default IGFX Primary Display PCIE Select which of IGFX/PEG/PCI Graphics device should be Primary Display. Auto Optimal Default, Failsafe Default Disable Internal Graphics...
  • Page 62 DisplayPort HDMI Select the Video Device which will be activated during POST. This has no effect of external graphics are present. Secondary boot display selection will appear based on your selection. VGA modes will be supported only on primary display Optimal Default, Failsafe Disable Detect Non-Compliance...

  • Page 63: Chipset: Memory Configuration

    3.5.3 Chipset: Memory Configuration Chapter 3 – AMI BIOS Setup...

  • Page 64: Setup Submenu: Boot

    Setup submenu: Boot Options summary: Disabled Quiet Boot Enabled Default Enables or disables Quiet Boot option Disabled Default Launch I217-LM PXE OpROM Enabled Enables or Disables Legacy Boot Option for I217-LM Disabled Default Launch I211-AT PXE OpROM Enabled Enables or Disables Legacy Boot Option for I211-AT Chapter 3 –...

  • Page 65: Setup Submenu: Security

    Setup submenu: Security Change User/Supervisor Password You can set a User Password once an Administrator Password is set. The password will be required during boot up, or when the user enters the Setup utility. Please Note that a User Password does not provide access to many of the features in the Setup utility. Select the password you wish to set, press Enter to open a dialog box to enter your password (you can enter no more than six letters or numbers).
  • Page 66 Removing the Password Highlight this item and type in the current password. At the next dialog box press Enter to disable password protection. Chapter 3 – AMI BIOS Setup...

  • Page 67: Setup Submenu: Save & Exit

    Setup submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 68: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 69: Product Cd/Dvd

    Product CD/DVD The VPC-5500S comes with a product DVD that contains all the drivers and utilities you need to setup your product. Insert the DVD and follow the steps in the autorun program to install the drivers. In case the program does not start, follow the sequence below to install the drivers.
  • Page 70 Drivers will be installed automatically Step 5 – Install LAN Drivers Open the Step 5 – LAN folder and select your OS Open the setup.exe file in the folder Follow the instructions Drivers will be installed automatically Step 6 – Install CAN Bus Driver (Windows 7 only) Go to Device Manager Expand the “Other Devices”...
  • Page 71 navigate to the drivers manually to install the drivers. Step 7 – Install RAID AHCI Driver Note: For Windows 7 users, please install NDP452-KB2901907-x86-x64-AllOS-ENU.exe (Microsoft.NET Framework) prior to installing the drivers. Open the Step 7 – RAID AHCI folder followed by SetupRST_13.6.0.1002.exe Follow the instructions Drivers will be installed automatically...
  • Page 72 Step 10 – Install UART Driver (Optional) Change User Account Control settings to Never notify Chapter 4 – Driver Installation...
  • Page 73 Reboot and log in as administrator Chapter 4 – Driver Installation...
  • Page 74 Run patch.bat as administrator Chapter 4 – Driver Installation...
  • Page 75 For Windows 8: Open the Apps Screen, right click on the Command Prompt tile and select Run as Administrator Chapter 4 – Driver Installation...
  • Page 76 To install the driver (patch.bat), you will first have to locate the file in command prompt. To do that, first go to the directory which contains the file by entering <drive letter>: eg. if the driver is in D drive, enter D: You are now at the directory containing the installation file.
  • Page 77 Chapter 4 – Driver Installation...

  • Page 78: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 79: Watchdog Timer Initial Program

    A.1 Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 80 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 81 ************************************************************************************ VOID Main(){ // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 82 ************************************************************************************ // Procedure : AaeonWDTEnable VOID AaeonWDTEnable (){ WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 1); // Procedure : AaeonWDTConfig VOID AaeonWDTConfig (){ // Disable WDT counting WDTEnableDisable(EnableLDN, EnableReg, EnableBit, 0); // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting(); VOID WDTEnableDisable(byte LDN, byte Register, byte BitNum, byte Value){ SIOBitSet(LDN, Register, BitNum, Value);...
  • Page 83 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...

  • Page 84: Appendix B - I/O Information

    Appendix B Appendix B - I/O Information...

  • Page 85: I/O Address Map

    I/O Address Map Appendix B – I/O Information...
  • Page 86 Appendix B – I/O Information...

  • Page 87: Memory Address Map

    Memory Address Map Appendix B – I/O Information...
  • Page 88 Appendix B – I/O Information...

  • Page 89: Irq Mapping Chart

    IRQ Mapping Chart Appendix B – I/O Information...
  • Page 90 Appendix B – I/O Information...
  • Page 91 Appendix B – I/O Information...
  • Page 92 Appendix B – I/O Information...

  • Page 93: Dma Channel Assignments

    DMA Channel Assignments Appendix B – I/O Information...

  • Page 94: Appendix C - Digital I/O Ports

    Appendix C Appendix C – Digital I/O Ports...

  • Page 95: Di/O Programming

    DI/O Programming VPC-5500S utilizes FINTEK F81866 chipset as its Digital I/O controller. Below are the procedures to complete its configuration. AAEON initial DI/O program is also attached for developing customized program for your application. There are three steps to complete the configuration setup:...

  • Page 96: Digital I/O Register

    Digital I/O Register Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Digital Input relative register table Register BitNum Value...

  • Page 97: Digital I/O Sample Program

    Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Digital Input Status relative definition (Please reference to Table 2) #define byte DInput1LDN // This parameter is represented from Note3 #define byte DInput1Reg // This parameter is represented from Note4...
  • Page 98 ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3) #define byte DOutput1LDN // This parameter is represented from Note27 #define byte DOutput1Reg // This parameter is represented from Note28 #define byte DOutput1Bit // This parameter is represented from Note29 #define byte DOutput1Val // This parameter is represented from Note30 #define byte DOutput2LDN // This parameter is represented from Note31 #define byte DOutput2Reg // This parameter is represented from Note32...
  • Page 99 ************************************************************************************ VOID Main(){ Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus(DInput3LDN, DInput3Reg, DInput3Bit); // Procedure : AaeonSetOutputLevel // Input : Example, Set Digital I/O Pin 6 level...
  • Page 100 ************************************************************************************ Boolean AaeonReadPinStatus(byte LDN, byte Register, byte BitNum){ Boolean PinStatus ; PinStatus = SIOBitRead(LDN, Register, BitNum); Return PinStatus ; VOID AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value){ ConfigToOutputMode(LDN, Register, BitNum); SIOBitSet(LDN, Register, BitNum, Value); ************************************************************************************ Appendix C – Digital I/O Ports...
  • Page 101 ************************************************************************************ VOID SIOEnterMBPnPMode(){ IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x87); VOID SIOExitMBPnPMode(){ IOWriteByte(SIOIndex, 0xAA); VOID SIOSelectLDN(byte LDN){ IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN); VOID SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData);...
  • Page 102 ************************************************************************************ Boolean SIOBitRead(byte LDN, byte Register, byte BitNum){ Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(LDN); IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= (1 << BitNum); SIOExitMBPnPMode(); If(TmpValue == 0) Return 0; Return 1; VOID ConfigToOutputMode(byte LDN, byte Register, byte BitNum){ Byte TmpValue, OutputEnableReg; OutputEnableReg = Register-1;...

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