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Shiratech Solutions Spark-100 Integration Manual

Altera cyclone v soc system on module
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Spark-100
Altera Cyclone V SOC
System on Module
Integration guide
Revision 1.3

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Summary of Contents for Shiratech Solutions Spark-100

  • Page 1 Spark-100 Altera Cyclone V SOC System on Module Integration guide Revision 1.3...

  • Page 2: Table Of Contents

    FPGA IOs ..........................23 2.5.3 Transceivers .......................... 23 2.5.4 FPGA configuration ....................... 23 2.6 HPS Memories scheme ........................24 2.6.1 QSPI NOR memory ........................ 25 2.6.2 EEPROM..........................25 2.6.3 eMMC (iNAND) ........................25 2 | Spark-100 HW user manual v1.3...
  • Page 3 Document Revision History Revision Date Description 12.6.2014 Initial version 15.8.2014 Fixing and updating various issues 1.11 7.9.2014 Update HPS voltage levels 16.11.2014 Add Qsys parameters 7.6.2015 Add description on pin variations between different FPGA sizes 3 | Spark-100 HW user manual v1.3...

  • Page 4: Scope

    Cortex-A9 cores combined with a large FPGA offering up to 110KLE. The Spark-100 enables the end user to create a tailored solution made of the ARM processor variety of interfaces combined with additional "Soft Core" interfaces based on the FPGA. The unique interconnection between the FPGA and ARM core enables the ARM processor to access the FPGA based interfaces as regular slave interfaces.

  • Page 5: Block Diagram

    The following diagram provides an overview of the SOM. The following paragraphs will provide detailed description of the various parts of the SOM and how to use them in order to build a product around it. Figure 1 – SOM main building blocks 5 | Spark-100 HW user manual v1.3...

  • Page 6: Spark-100 Integration Guide

    BSP development phase and reduce the risk of mistakes. The reference design is based on the CB-50. 2.1 Power considerations The Spark-100 uses a single 5V power input from which all the other required voltages are taken.?. The Inlet power should be ...

  • Page 7: Bank 3B And 4A - Programmable Power Levels

    The power of banks 3B and 4A can be programmed according to the design requirements. Each bank in the FPGA has a VCCPD and a VCCIO that control the banks power level. Banks 3B and 4A share a single 7 | Spark-100 HW user manual v1.3...
  • Page 8 Switch DC to DC Power 3.3, 2.5, 1.8V Switch VCCIO Programmable VCCIO Bank 4A Bank 4A 1.5V, 1.8V, 2.5V, 3.3V 0.6A Power 1.5V FPGA Switch Figure 3 - Bank 3B/4A Power Switching scheme 8 | Spark-100 HW user manual v1.3...
  • Page 9 Setting the power levels via the internal switches The power levels of ports 3B and 4A can be set by dip switches located on the SPARK-100 board (SW2). There is a single switch that sets the VCCPD power for both banks and two switches that set the power of the VCCIO for each bank.

  • Page 10: Bank3A And Bank4A Vref

     Debug Reset o Occurs after HPS has already been through a cold reset o Used to recover debug logic from a non-responsive condition o Only affects the debug reset domain 10 | Spark-100 HW user manual v1.3...
  • Page 11 When using the 128 MB QSPI Flash memory as a boot source the warm reset does not work automatically due to configuration issues of the QSPI memory. For more details: http://www.rocketboards.org/foswiki/Documentation/SocBoardQspiBoot For 32MB QSPI Flash memory configuration the problem is resolved. 11 | Spark-100 HW user manual v1.3...

  • Page 12: Hps Interfaces

    2.3 HPS Interfaces The Spark-100 offers a variety of interfaces from the HPS (SOC ARM core) such as USB, Ethernet, I2C, SPI, UART and more. The following paragraphs describe the various interfaces available along with recommendations on how to connect them to the carrier board.

  • Page 13: Ethernet Port

    USB power distributer located on the carrier board. 2.3.2 Ethernet port The SPARK-100 supports a single 10/100/1000 Ethernet interface from the HPS (RGMII 1). The Ethernet Phy in connected via an RGMII interface to the HPS. The following figure describes the Giga Ethernet interface.

  • Page 14: I2C Overview

     DMA controller may be used for large transfers. 2.3.5 I2C overview The Spark-100 uses two I2C buses of the HPS. The HPS offers the following I2C support: Maximum clock speed of up to 400 Kbps. 7- or 10-bit addressing.

  • Page 15: I2C Mapping

    I2C_GP in SMARC standard I2C_PM_D Enables access to I2C devices on Carrier I2C_PM _C I2C_PM in SMARC standard I2C_LCD_D Enables access to I2C devices on Carrier I2C_LCD _C I2C_LCD in SMARC standard Not Connected 15 | Spark-100 HW user manual v1.3...
  • Page 16 SATA is active (When available) "0" – Off "1" – on INT1_A On board debug Led "0" – off "1" – On 2.3.6.3 I2C Address table The following table describes the I2C addresses mapping: 16 | Spark-100 HW user manual v1.3...

  • Page 17: Spi

    Note – When the SPI interfaces are not in use, the pins can be configured as a GPIOs. 2.3.8 JTAG The SPARK-100 integrates an optional on board 10 pins JTAG connector. The JTAG signals are also connected to the SMARC connector, an analog switch selects between the JTAG connector and the SMARC connector.
  • Page 18 1 FPGA not in chain JSEL1 0 JTAG connector (default) 1 SMARC connector Note: For production, the SOM provided without the JTAG connector; in that case the JTAG interface will be available only on the SMARC interface. 18 | Spark-100 HW user manual v1.3...

  • Page 19: Clocks Scheme

    2.4 Clocks scheme The SPARK-100 supports two clock schemes Basic – available when SOC SE devices are assembled or Advanced – available when SOC SX devices are assembled. 2.4.1 Basic clock architecture – SE SOC devices This option is provided for SE devices. In that case an internal 25 MHz clock is used for driving the HPS clock inputs, it also provides two clock sources for the FPGA.
  • Page 20 – Pin V4 Y1_P – Pin 17 SMARC interface - Clock out to carrier board PCIE_A_REFCK+ - Pin P83 Y1_N – Pin 16 SMARC interface Clock out to carrier board PCIE_A_REFCK- - Pin P84 20 | Spark-100 HW user manual v1.3...
  • Page 21 Y7_N – Pin 36 Altera device – FPGA clock input. CLK4N – Pin W24 Note: If a single ended clock is required only the P line of the clock should be used. 21 | Spark-100 HW user manual v1.3...

  • Page 22: Fpga

    I/Os and optionally additional 6 high speed transceivers. 2.5.1 FPGA IOs variation The Spark-100 support several SOC variations starting from 25KLE and up to 110KLE for both SE and SX series. Altera offers the same package for all variations however there are differences between the pin out of the different FPGA sizes.

  • Page 23: Fpga Ios

    The FPGA file should be in FPP 16(Fast parallel 16 bits), security disable, compression disable, RBF format, the file should be called fpga.rbf. The FPGA will be programed by the boot software, 23 | Spark-100 HW user manual v1.3...

  • Page 24: Hps Memories Scheme

    '0' 2.6 HPS Memories scheme The SPARK-100 includes several options for non-volatile memories for booting and data storage, including: A QSPI NOR memory (32MB or 128MB), can be used for a small footprint Linux version or RTOS.

  • Page 25: Qspi Nor Memory

     Up to 108MHz clock.  Two ordering option 128Mbytes and 32Mbytes. 2.6.2 EEPROM The Spark-100 is supports an internal I2C memory device Atmel AT24C01Ce, located on I2C1 bus of the HPS offering:  1Kbit I2C memory.  Can be used as secure boot.

  • Page 26: Sd/Emmc Interface

    2.6.4 SD/eMMC interface The SPARK-100 has a single SD/MMC bus connected to the HPS. The HPS is connected via an internal multiplexer (TXS02612 - SDIO Port Expander by TI) to either an internal 4/8 bits wide eMMC or to an external 4 bits SD interface.

  • Page 27: Interrupt & I/O Table

    The Spark has a build in temperature sensor based on TI Digital Temperature Sensor TMP 108. The device is controlled via I2C1 bus. 2.9 Pin assignment The connector offers 314 pins which are used for:  Power  GPIOs 27 | Spark-100 HW user manual v1.3...
  • Page 28 Fixed interfaces like GE and USB  RFU - unused pins reserved for future use. The full pin out of the Spark is available in a dedicated document “SPARK pin out definition” available on the Shiratech web site. 28 | Spark-100 HW user manual v1.3...

  • Page 29: Mechanical Considerations

    The following figures are taken from the standard to show the physical dimensions of the module and the required layout of the carrier board. Note that the Spark is using the smaller option of 82x50. 29 | Spark-100 HW user manual v1.3...

  • Page 30: Smarc Connector

    AS0B821-S43N - *H 1.5mm 4.3mm Flash Ivory Foxconn AS0B826-S43B - *H 1.5mm 4.3mm 10 u-in Black Foxconn AS0B826-S43N - *H 1.5mm 4.3mm 10 u-in Ivory Foxconn AS0B821-S55B - *H 2.7mm 5.5mm Flash Black 30 | Spark-100 HW user manual v1.3...
  • Page 31 AS0B821-S78B - *H 5.0mm 7.8mm Flash Black Foxconn AS0B821-S78N - *H 5.0mm 7.8mm Flash Ivory Foxconn AS0B826-S78B - *H 5.0mm 7.8mm 10 u-in Black Foxconn AS0B826-S78N - *H 5.0mm 7.8mm 10 u-in Ivory 31 | Spark-100 HW user manual v1.3...

  • Page 32: Appendix 1 - Hardware Devices Used On The Som

    TMP108 Low Power Digital Temperature Sensor With Two-Wire Serial Interface in WCSP TCA9548A Low voltage 8-channel I2C switch USB2422 Microchip 2-Port USB 2.0 Hi-Speed Hub Controller KSZ9031RN Micrel 1G Ethernet Physical layer chip 32 | Spark-100 HW user manual v1.3...

  • Page 33: Appendix 2 - Qsys Parameters For The Spark

    Appendix 2 – Qsys parameters for the Spark The following paragraph provides the HPS configuration used in the demo version provided for the Spark. 33 | Spark-100 HW user manual v1.3...
  • Page 34 USB, GE, I2C etc… For interfaces which are connected directly connected to Spark interface, the configuration is open, can should be taken to the power level provided to these interfaces. 34 | Spark-100 HW user manual v1.3...
  • Page 35 Clock configuration: 35 | Spark-100 HW user manual v1.3...
  • Page 36 DDR setting: 36 | Spark-100 HW user manual v1.3...
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