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Shiratech Solutions AT-501 Integration Manual

Cortex-a5 system on module
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AT-501
Cortex-A5
System on Module
Integration guide
Revision 1.4

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Summary of Contents for Shiratech Solutions AT-501

  • Page 1 AT-501 Cortex-A5 System on Module Integration guide Revision 1.4...

  • Page 2: Table Of Contents

    Port B options ........................27 2.5.4 Port C options ........................28 2.5.5 Port D options ........................29 2.5.6 Port E options ........................30 AT-501 System overview ........................31 3.1 Cortex-A5 Processor ........................31 3.2 Memories ............................31 2 | AT-501 HW user manual 1.4...
  • Page 3 Add D36, update USART capabilities. 1.6.2014 Add notes about OTG support; add details about components height on the print side. 6.4.2015 Fix debug port pin out 26.8.2015 Add remarks about VBAT and Resistive touch interfaces 3 | AT-501 HW user manual 1.4...

  • Page 4: Scope

    1 Scope The purpose of this document is to provide a guide for integrating the AT-501 into the target hardware in an easy and fast way so that the use of SoM will shorten and simplify the development process. The guide is divided to two parts, the first one help you through the integration process, giving design samples based on the design of the CB-20(schematics can be provided by Shiratech via support@shiratech.com...
  • Page 5 Figure 1 – Interface support on the various SAMA5D3 processors 5 | AT-501 HW user manual 1.4...

  • Page 6: At-501 Integration Guide

    2.1 Power connectivity The AT-501 uses a single power input of 3.3V from which all the other required voltages are taken. The 3.3V input is only directly used for power the processor I/Os. The Inlet power should be ...
  • Page 7 The AT-501 has an optional backup power source for the Real-Time-Clock. It can support an approximately 1 hour of the RTC operation when the main power fails. The following figure describes the AT-501 backup power.

  • Page 8: Reset

    WakeUp Shutdown Inlet Figure 3 – AT-501 Backup Power scheme 2.2 Reset The NRESET signal is an open-drain interface. It generates a reset on POR or on a reset event generated by the SW. It also can be used as an input to an external reset source like a push-button.

  • Page 9: Interfaces

    2.3.1.1 Giga Ethernet port The AT-501 includes a build in 1GE interface (including physical layer chip) in all it models except the one which includes the SAMA5D31 which does not support GE. The Physical layer chip is connected via MDC/MDIO interface using the default PHY address is 0001 for both interfaces.

  • Page 10: Uart And Usart

    The MDC frequency is derived from the system clock and should not exceed 2.5MHz. 2.3.2 UART and USART There are up to four USART and two UART interfaces dependent on PIO utilization and processor type. The following paragraph describes the various options. 10 | AT-501 HW user manual 1.4...
  • Page 11 By-8 or by-16 Over-sampling Receiver Frequency o Optional Hardware Handshaking RTS-CTS  RS485 with Driver Control Signal  IrDA Modulation and Demodulation Note: the USART can be used as SPI interface if required. 11 | AT-501 HW user manual 1.4...

  • Page 12: Usb

    Note: For automatic detecting of the external device connected it is recommended to use the ID pin of the USB interface and to connect it to a GPIO of the processor. o This port should be used for connecting by the Atmel SAM-BA tool. 12 | AT-501 HW user manual 1.4...
  • Page 13 Port-C supports USB 2.0 Host interface. The SAMA5D3 integrates the USB PHY so there is no need for external devices. To be compatible with the AT-501 SW the following I/O need to be connected when using the USB interfaces: •...

  • Page 14: High Speed Multi-Card Interface

    SAMA5D3 MCI0 through the edge connector. The Micro-SD powered by a 3.3V power supply. Figure 1 – Micro SD card implementation on the CB-20 2.3.5 LCD and touch screen support The SAMA5D3 support an internal LCD controller with build in support for resistive touch screen. 14 | AT-501 HW user manual 1.4...
  • Page 15 The touch interface is using AD(0-4) which are available over pins 181-185 in the SO-DIMM connector. See below touch screen connectivity sample for the CB-20 Figure 10 – Touch screen connectivity example Note: if these pins are not used, they are set to inputs with internal pull up. 15 | AT-501 HW user manual 1.4...

  • Page 16: Can

    2.3.6 CAN The AT-501 supports up to two CAN interfaces depending on the processor type (available only on the D34 and D35). The CAN interfaces are available under the following constrains:  CAN 0 - If USART 0 CTS, SCK are used or if SPI0-CS(1-2) then CAN 0 cannot be used.

  • Page 17: Jtag

    2.3.10 JTAG The AT-501 has a JTAG interface that can be used either for JTAG testing or for connecting an ICE. The selection between the two modes is done using setting JTAGSEL pin 8 in the SO-DIMM connector to the right mode.
  • Page 18 Figure 12 – AT-501 CS view The height of devices in the PS is up to 1mm with the exception of U22 which is 1.4mm. Figure 13 – AT-501 PS view The supporting holes diameter is 3mm. 18 | AT-501 HW user manual 1.4...

  • Page 19: So-Dimm Connector

    2.4.1 SO-DIMM connector The AT-501 uses an SO-DIMM interface for connecting the SOM. The carrier board should use a 1.8V DDR2 SO-DIMM connector. The connector comes in different heights according the need. In the CB-20 the SO-DIMM connector is 1473005-4 from TE connectivity. Any other compatible connector can be used.
  • Page 20 Integrated pull up on the SoM if not required leave open Not used Not used Not used Not used PE16 GPIO PE17 GPIO PE18 GPIO PE19 GPIO PE20 GPIO 20 | AT-501 HW user manual 1.4...
  • Page 21 3.3V power PA20 GPIO PA21 GPIO PA18 GPIO PA19 GPIO PA16 GPIO PA17 GPIO PD14 GPIO PD15 GPIO PD16 GPIO PB12 GPIO PB23 GPIO Ground PB21 GPIO PB24 GPIO PB19 GPIO PB22 GPIO 21 | AT-501 HW user manual 1.4...
  • Page 22 PB27 GPIO PB26 GPIO PB10 GPIO Ground PD10 GPIO PD11 GPIO PD12 GPIO PD13 GPIO Ground Not used PC22 GPIO PC25 GPIO PC23 GPIO PC24 GPIO PA31 GPIO PA30 GPIO Ground GPIO GPIO 22 | AT-501 HW user manual 1.4...
  • Page 23 GPIO GPIO GPIO GPIO Ground GPIO GPIO GPIO GPIO PA10 GPIO PA11 GPIO Ground PA12 GPIO PA13 GPIO PA14 GPIO PA15 GPIO Ground PC14 GPIO PC13 GPIO PC12 GPIO PC11 GPIO PC10 GPIO 23 | AT-501 HW user manual 1.4...
  • Page 24 PD21 GPIO PD22 GPIO PD23 GPIO PD24 GPIO When using USB port A, this pin is PD29 USB-A GPIO used for power sense over current sense from all USB PD28 GPIO ports Ground 24 | AT-501 HW user manual 1.4...
  • Page 25 A/D, if not used ADVREF Power connect to 3.3V Ground ET0-Tx2+ GMAC ET0-Tx1+ GMAC ET0-Tx2- GMAC ET0TX1- GMAC ET0RX2+ GMAC ET0RX1+ GMAC ET0RX2- GMAC ET0RX1- GMAC GND ETH Ground 25 | AT-501 HW user manual 1.4...

  • Page 26: Port A Options

    PA21 LCD-DA21 - Not PA21 PWML0 ISI_D5 used PA22 LCD-DA22 - Not PA22 PWMH1 ISI_D6 used PA23 LCD-DA23 - Not PA23 PWML1 ISI_D7 used PA24 PA24 LCD-PWM PA25 PA25 LCD-DISP PA26 PA26 LCD-VSYNC 26 | AT-501 HW user manual 1.4...

  • Page 27: Port B Options

    Not available G125CK PB19 PB19 MCI1_CDA GTX4 PB20 PB20 MCI1_DA0 GTX5 PB21 PB21 MCI1_DA1 GTX6 PB22 PB22 MCI1_DA2 GTX7 PB23 PB23 MCI1_DA3 GRX4 PB24 PB24 MCI1_CK GRX5 PB25 PB25 USART1 - SCK1 GRX6 27 | AT-501 HW user manual 1.4...

  • Page 28: Port C Options

    PC17 SSC0-TF PC18 PC18 SSC0-TD PC19 PC19 SSC0-RK PC20 PC20 SSC0-RF PC21 PC21 SSC0-RD PC22 PC22 SPI1_MISO PC23 PC23 SPI1_MOSI PC24 PC24 SPI1_SPCK PC25 PC25 SPI1_NPCS0 PC26 PC26 SPI1_NPCS1 I2C1 - TWD ISI_D11 28 | AT-501 HW user manual 1.4...

  • Page 29: Port D Options

    PD21 AD1 - touch screen PD22 PD22 AD2 - touch screen PD23 PD23 AD3 - touch screen PD24 PD24 AD4 - touch screen PD25 PD25 PD26 PD26 PD27 PD27 PD28 PD28 PD29 PD29 29 | AT-501 HW user manual 1.4...

  • Page 30: Port E Options

    PE24 PE24 USART2 -RTS PE25 1 wire USART2 -RXD PE26 PE26 NCS0 USART2 -TXD PE27 PE27 NCS1 TIOA2 LCD-DAT22 PE28 PE28 NCS2 TIOB2 LCD-DAT23 PE29 PE29 NWR1/NBS1 TCLK2 PE30 PE30 NWAIT PE31 PWML1 30 | AT-501 HW user manual 1.4...

  • Page 31: At-501 System Overview

    3 AT-501 System overview 3.1 Cortex-A5 Processor The AT-501 uses Atmel's SAMAD5 ARM Cortex-A5 based CPU as the modules controller. The SAMA53 is a family of CPU which implement the ARMv7 architecture and run 32 bits instructions. It includes an FPU (Not NEON) which is tightly integrated into the processor pipeline.
  • Page 32 SAM-A5 Boot Figure 13 – AT-501 Memory eMMC (iNAND) – optional The AT-501 can be equipped with 4 or 8 GB eMMC device. The device can be used both for data and software.  Uses the SAMAD5 MCI0 interface. ...
  • Page 33 Note: The one-wire chip contains information about the board, this information should not be changed by the end user. In case the information will be changed warranty will not be available for the module. 33 | AT-501 HW user manual 1.4...

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