D-Board (1 Of 2) Block Diagram - Panasonic TH-50PZ750U Service Manual

TH-50PZ750U

15.42. D-Board (1 of 2) Block Diagram

D FORMAT CONVERTER,
P+15V
IC9806
P+5V
+5V
P+5V
TO P25 D25
P+15V
1
P+15V
2
P+15V
P+5V
7
P+5V
9
P+5V
STB+5V
10
STB+5V
13
F_STB_ON
ECO_ON 15
SOS
PS_SOS 16
MAIN
PANEL_ON 17
ALL_OFF 18 P_CTL
VAD
20
Vda_Low
TO DG35
D3
R3134
IIC_CTL
IIC_CONT 1
IIC/INT
IIC/INT 2
SCLK2
IIC_CLK2 3
SDA2
IIC_DATA2 4
MUTE
DISPEN 6
P_STATUS
D9802
READY 7
P_SOS
ALARM 8
P_CTL
PANEL_STBY_ON 11 D9811
STB5V 12
D9804
RXD
RXD 14
P15V 15 IIC/INT
TXD
TXD 16
ECO ON 18
SCLK1
IIC_CLK1 19
SDA1
IIC_DATA1 20
PDB1
PDB1 21
PSLCT
PSLCT 22
PDB0
PDB0 23
PBUSY
PBUSY 25
PSTB
PSTB 26
ALL_OFF 27
F_STB_ON 29
D6 1 2 4 5 6 7 8 9 10 11 12 13
FOR
FACTORY USE
TH-50PZ750U
D-Board (1 of 2) Block Diagram
PLASMA AI PROCESSOR
P+3.3V P+1.2V
IC9807
Q9803
P+3.3V
IC9801
P+3.3V
P+1.5V
+3.3V
P+3.3V
P+1.5V
+1.5V
IC9809 P+1.5V
PANEL POWER PART SOS DET
Q9801
P+15V OVER VOLTAGE LED BLINKING
P+2.5V
P+3.3V FAIL VOLTAGE LED BLINKING
P+5V FAIL VOLTAGE LED BLINKING
P+2.5V
+2.5V
R9217 R9218
P+2.5V
R9215
IC9800
R9207
Q9800
R9219
P+1.2V
Q9051 Q9052
P+1.2V P+15V SOS DET
R9203
+1.2V
P+1.2V
IC9011
Q9046
STB+3.3V
STB+3.3V/RESET
ON/OFF
R9127
R9141
Q9044
6
STB+3.3V STB+3.3V
STB+5V
ON/OFF
4 +3.3V 3
RESET 1
R9871 R9868
P+3.3V
D9808
Q9805
D9807 R9869
R9870
Q9806
P+1.2V/+1.5V/+2.5V/+3.3V
ON/OFF
P+15V
14 15 16 17 18 19 21
2 TIMES
3 TIMES
5 TIMES
STB+3.3V
D9020 R9220 R9221
P+5V
R9205
69 P+5V SOS DET
R9206
IC9003
R9222
Q9053 Q9054 MCU
P+5V SOS DET
70 P+3.3V SOS DET
71 P+15V SOS DET
9 RESET
14 IIC/INT
IIC/INT
6
SCLK2
STB 15 IIC_CTL
IIC_CTL
+3.3V
5
26 S CLOCK2
SDA2
SCLK2
27 S DATA2
SDA2
IC9001
28 TXD
TXD
EEPROM
29 RXD
(64k)
RXD
50 S CLOCK1
SCLK1
51 S DATA1
SDA1
1
SCLK2
P+3.3V
X9000
6
SDA2
27MHz
10
IC9002 OSC
12
TEMP SENSOR
Q9010
INV. 16 REMOTE
68 5 23 24 65 66 67
D5 1 2 4 5 6 7 9 10 11 12 14
TO DH5
118
P+1.2V P+3.3V
VIDEO SIGNAL PROCESSOR
P+2.5V P+3.3V
P+1.5V
E+ LVDS0
E- LVDS0
E+ LVDS1
E- LVDS1
E+ LVDS2
E- LVDS2
E+ LVDS3
E- LVDS3
E+ LVDS4 LVDS
E- LVDS4 RX
E+ LVDSCLK
E- LVDSCLK
TTL
O+ LVDSCLK PARALLE
DATA
O- LVDSCLK
O+ LVDS0 HD
O- LVDS0
VD
O+ LVDS1
O- LVDS1
O+ LVDS2
O- LVDS2
3
O+ LVDS3
STB+3.3V
O- LVDS3
O+ LVDS4
O- LVDS4
LVDS_DET
LVDS_DET
6 2 5 1
NCS 36 NCS
ASDIO 37 ASDIO
DATA0 38 DATA0
DISCHARGE
DCLK 39 DCLK
CONTROL
DRV_MUTE 18 DRV_MUTE
DRIVER RESET 20 DRIVER RESET
IC9007
EEPROM(FPGA)
(1MB)
IIC
CONT
74 72 76 73
Q9401
INV
15 16 17 18 20 21 23 24 25 26 28 29 30 31
TH-50PZ750U
D-Board (1 of 2) Block Diagram
P+2.5V
1
2
3
IC9500
4
R 10bit
5
G 10bit 6
B
10bit
RGB
R 10bit
7
G 10bit
8
B 10bit
9
HD,VD HD,VD
10
SYNC
PROCESSOR
HD,VD HD,VD
11
BUS SW 12
13
DATA CONTROL(U)
DATA CONTROL(D) 14
SUS CONTROL 15
16
SCAN CONTROL
17
18
19
20
21
22