Status Byte Register (Sbr) - Agilent Technologies 54621A Programmer's Manual

Mixed-signal oscilloscopes
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Status Reporting

Status Byte Register (SBR)

Status Byte Register (SBR)
The Status Byte Register is the summary-level register in the status reporting
structure. It contains summary bits that monitor activity in the other status
registers and queues. The Status Byte Register is a live register. That is, its
summary bits are set and cleared by the presence and absence of a summary
bit from other event registers or queues.
If the Status Byte Register is to be used with the Service Request Enable
Register to set bit 6 (RQS/MSS) and to generate an SRQ, at least one of the
summary bits must be enabled, then set. Also, event bits in all other status
registers must be specifically enabled to generate the summary bit that sets the
associated summary bit in the Status Byte Register.
The Status Byte Register can be read using either the *STB? Common Command
or the GPIB serial poll command. Both commands return the decimal-weighted
sum of all set bits in the register. The difference between the two methods is
that the serial poll command reads bit 6 as the Request Service (RQS) bit and
clears the bit which clears the SRQ interrupt. The *STB? command reads bit 6
as the Master Summary Status (MSS) and does not clear the bit or have any
affect on the SRQ interrupt. The value returned is the total bit weights of all of
the bits that are set at the present time.
The use of bit 6 can be confusing. This bit was defined to cover all possible
computer interfaces, including a computer that could not do a serial poll. The
important point to remember is that, if you are using an SRQ interrupt to an
external computer, the serial poll command clears bit 6. Clearing bit 6 allows
the oscilloscope to generate another SRQ interrupt when another enabled event
occurs.
No other bits in the Status Byte Register are cleared by either the *STB? query
or the serial poll, except the Message Available bit (bit 4). If there are no other
messages in the Output Queue, bit 4 (MAV) can be cleared as a result of reading
the response to the *STB? command.
If bit 4 (weight = 16) and bit 5 (weight = 32) are set, the program prints the
sum of the two weights. Since these bits were not enabled to generate an SRQ,
bit 6 (weight = 64) is not set.
6-8

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