While the SP7650 Evaluation Board has been tested and delivered with the output set to 3.30V, by simply changing one resistor, R2, the SP7650 can be set to other output voltages. The relationship in the following formula is based on a voltage divider from the output to the feedback pin VFB, which is set to an internal reference voltage of 0.80V.
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+5V BIAS SUPPLY APPLICATION SCHEMATIC In this application example, the SP7650ER is power by an external +5V bias supply which current consumption of 20mA Maximum. If this supply is not available than it is recommend Sipex SPX5205 Low-Noise LDO Voltage Regulator. SP7650 VOUT PGND 6.8uH...
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Definitions: Resr := Output Capacitor Equivalent Series Resitance := Output Inductor DC Resistance Vramp_pp := SP7650 Internal RAMP Amplitude Peak to Peak Voltage Conditions: Cz2 >> Cp1 and R1 >> Rz3 Output Load Resistance >> Resr and Rdc Figure 11. Voltage Mode Control Loop with Loop Dynamic for Type III Compensation...
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Select L = 6.8uH => yield ≈ 40% of maximum 3A output current ripple. Select Cout = 22uF Ceramic capacitor (Resr ≈ 4mΩ) fs = 300khz SP7650 internal Oscillator Frequency Vramp_pp = 1.0V SP7650 internal Ramp Peak to Peak Amplitude Step by step design procedures: fco = 300khz / 5 = 60khz fp_LC = 1 / 2π...
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+5V INPUT WITH A TYPE III COMPENSATION APPLICATION SCHEMATIC Figure 12 shows another example of SP7650ER configures for +5V input by simply changing a few external resistors and capacitors components value for delivering a 0- 3A output with excellent line and load regulation. SP7650 VOUT PGND 3.30V 6.8uH...
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PC LAYOUT DRAWINGS Figure 13. SP7650EB Component Placement Figure 14. SP7650EB PC Layout Top Side Figure 15. SP7650EB PC Layout 2 Layer Side...
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Figure 16. SP7650EB PC Layout 3 Layer Side Figure 17. SP7650EB PC Layout Bottom Side...
Table 2: SP7650EB List of Materials 8700 8700 ORDERING INFORMATION Model Temperature Range Package Type SP7650EB…........-40°C to +85°C....…SP7650 Evaluation Board SP7650ER......…. -40°C to +85°C.........……26-pin DFN...
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