Epson S5U1C33001H Manual page 6

S5U1C33001H
DIP Switches
Note: Before setting the DIP switch, be sure to turn off the power to the S5U1C33001H.
The DIP switch assembly on the S5U1C33001H front panel is used to set the following conditions: DCLK setting, flash
programmer mode, target connection diagnostic function, flash programmer verification mode, and DSIO output level.
The figure below shows an external view of the DIP switch assembly.
• Flash programmer mode setting
DIP switches 1 and 7 enable/disable the flash programmer mode.
SW1
OPEN
OPEN
ON
ON
• DCLK - core clock ratio setting
DIP switches 2 and 3 set the ratio of the DCLK to the core clock frequencies.
SW2
OPEN
OPEN
ON
ON
These switches set the DCLK - core clock ratio while the program execution is halted. Select an appropriate value so
that the DCLK frequency will not exceed 40 MHz. If DCLK exceeds 40 MHz, the S5U1C33001H will not be able to
communicate with the target system normally; it may result in a target system failure.
While the program is being executed, the DCLK is set to the same frequency with the core clock. The upper-limit
frequency in this case is 100 MHz to perform tracing. There is no limit when tracing is not performed.
• Trace function setting
DIP switches 4 and 5 enable/disable the trace function.
SW4
OPEN
OPEN
ON
ON
• Target system connection diagnostics setting
DIP switch 6 selects whether the target system connection diagnostics function is used or not.
SW6
OPEN
ON
• DSIO output level setting
DIP switch 8 sets the DSIO output level.
SW8
OPEN
ON
6
(Ver. 4)
1 2 3
Figure 4 DIP Switch
Table 3 DIP SW1 and SW7 Settings
SW7
OPEN Flash programmer mode disabled (default)
ON Flash programmer mode disabled
OPEN Flash programmer mode enabled (erase and write mode)
ON Flash programmer mode enabled (verify mode)
Table 4 DIP SW2 and SW3 Settings
SW3
OPEN 1/4 core clock (default)
ON 1/2 core clock
OPEN 1/1 core clock
ON 1/8 core clock
Table 5 DIP SW4 and SW5 Settings
SW5
OPEN PC trace enabled, bus trace disabled (default)
ON PC trace disabled, bus trace disabled
OPEN PC trace enabled, bus trace enabled
ON Illegal value
Table 6 DIP SW6 Setting
The target system connection test is run when the debugger is started. (default)
The target system connection test is omitted when the debugger is started.
Table 7 DIP SW8 Setting
DSIO output level: 3.3 V (default)
DSIO output level: 1.8 V
OPEN
4 5 6 7 8
ON
Setting
Setting
Setting
Setting
Setting