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S5U1C33001H
PRECAUTIONS
Restrictions on Debugging
The debugging using the S5U1C33001H is subject to the restrictions specified below.
• Operation of the internal peripheral circuits
The peripheral circuits of the S1C33xxx stop operating when the debugger (gdb.exe) on the host computer is ready to
accept commands, that is, unless the target program is running. For this reason, the peripheral circuits do not operate in
real time when the target program is executed in the single-step mode. For details on single-step execution, refer to the
"Debugger" section in the "S5U1C33001C Manual (C Compiler Package for S1C33 Family)".
• Interrupts when the target program is not running
If an interrupt request to the C33 core is generated by the target system when the target program is not running, interrupt
processing is paused. The interrupt that has been paused is serviced immediately before the target program is executed
or immediately after one instruction is executed after the debugger (gdb.exe) on the host computer has directed that the
target program be executed.
• Interrupts when the target program is executed in a single step
If an interrupt request to the C33 core is generated by the target system during single-step execution of the target
program, including functions and subroutines (STEP), the interrupt request is paused. During single-step execution of
the target program, not including functions and subroutines (NEXT), an interrupt request received within a function or
subroutine is serviced without being paused and an interrupt received in other parts of the program is paused as with the
STEP command. The interrupt that has been paused is serviced immediately before the target program is executed or
immediately after one instruction is executed after the debugger (gdb.exe) on the host computer has directed that the
target program be executed. For details on single-step execution (STEP and NEXT), refer to the "Debugger" section in
the "S5U1C33001C Manual (C Compiler Package for S1C33 Family)".
• Break functions
The S5U1C33001H and the debugger support multiple break functions.
The timing at which a break occurs is classified into the following two categories depending on the break function.
(1) Break functions that suspend the target program before the instruction in which the cause of the break occurred is
executed
Software PC break, hardware PC break
(2) Break functions that suspend the target program after several instructions are executed from the instruction in which
the cause of the break occurred
Data break, area break, bus break
For details on break functions, refer to the "Debugger" section in the "S5U1C33001C Manual (C Compiler Package for
S1C33 Family)".
• Trace function
Note that the trace function in the S5U1C33001H has the following restrictions. Furthermore, refer to the technical
information of the trace function ("Implementation of the PC Trace Function" and "Implementation of the Bus Trace
Function").
(1) The S5U1C33001H PC trace function can trace only instruction execution cycle information. Note that data access
(read/write) information cannot be traced. When the target system uses the S1C33 model in which a C33 core that
supports the bus trace function is embedded, data read/write information can be traced.
(2) Be aware that the trace function cannot be used when it is disabled using the DIP switch. For enabling/disabling the
trace function using the DIP switch, refer to "Trace function setting" in the "DIP Switches" section.
(3) There are certain functional limitations to the PC trace function that are due to the analysis procedure being imple-
mented in software. Refer to "Implementation of the PC Trace Function" section and the "S5U1C33001C Manual (C
Compiler Package for S1C33 Family)" for more information.
(4) Be aware that the trace function cannot be used when using the 4-pin cable to connect the target system to the
S5U1C33001H.
(5) Be aware that the bus trace function cannot be used when using the 10-pin cable to connect the target system to the
S5U1C33001H.
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(Ver. 4)
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