Telit Wireless Solutions JF2 Hardware User's Manual
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Telit Wireless Solutions JF2 Hardware User's Manual

Telit Wireless Solutions JF2 Hardware User's Manual

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JF2 Hardware User Guide
1vv0300985 Rev.4 2013-04-09

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Summary of Contents for Telit Wireless Solutions JF2

  • Page 1 JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09...
  • Page 2 JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 APPLICABILITY TABLE PRODUCT Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved. Page 2 of 40 Mod. 0805 2011-07 Rev.2...
  • Page 3 JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Notice While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein.

  • Page 4: Vv0300985 Rev.4 2013

    JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 Usage and Disclosure Restrictions License Agreements The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.

  • Page 5: Table Of Contents

    Contact Information, Support ..................8 Document Organization ....................9 1.4. 1.5. Text Conventions ......................9 Related Documents ......................9 1.6. Powering the JF2 ....................10 2.1. 1.8V Supply Voltage ....................10 2.1.1. Capacitance ........................ 10 2.2. Implementing Pseudo Battery Back-up ..............10 2.3.
  • Page 6 JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 MEMS Sensor/EEPROM Interface ..............21 RF Front End Design ..................22 9.1. RF Signal Requirements ..................22 9.2. GPS Antenna Polarization ..................24 9.3. GPS Antenna Gain ....................24 9.4. System Noise Floor ....................25 9.5.
  • Page 7 JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 11.5.1. Static Navigation ..................... 34 11.5.2. Velocity Dead-Reckoning ..................34 11.5.3. MEMS Static Detection ................... 35 11.5.4. MEMS Wake-up ...................... 35 11.6. Advanced Features....................35 11.6.1. CW Jamming Detection ..................35 11.6.2. SBAS ........................35 11.6.3.

  • Page 8: Introduction

    Introduction 1.1. Scope The JF2 is an 11mm by 11mm integrated GPS receiver module using SiRFstar IV technology. This document expands upon the data sheet(s) to highlight particular areas to allow the hardware engineer to achieve a successful design implementation.

  • Page 9: Document Organization

    “Chapter 2: “Powering the JF2” gives an overview about power supply. “Chapter 3: “Example Implementations” describes examples on how to implement the JF2. “Chapter 4: “Updating Firmware” describes the SW updating procedure for Flash version. “Chapter 5: “Updating Patch code”...

  • Page 10: Powering The Jf2

    A logic low indicates the module is in “hibernate”, whereas logic high indicates the module is in “operate” state. If the 1.8 volt DC supply is removed from the JF2 (regardless of power state) it will lose current RTC time and will lose the contents of the internal SRAM. To prevent improper startup, once power is removed, keep the power removed for approximately 10 seconds so the internal SRAM contents can clear reliably.

  • Page 11: Understanding On-Off And System-On

    ON-OFF: Input control SYSTEM-ON: Output indicator The JF2 power is controlled by a state machine. This state machine is clocked by the internal 32 KHz RTC clock, and is controlled by internal signals as well as the ON-OFF and NRESET signals.
  • Page 12 JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 VDD 18 (clock runs) RTC CLK (INTERNAL) HIGH Unknown ON-OFF Unknown SYSTEM-ON Figure 1 – Initial Application of Main Power Timed Prior Symbol Unit Parameter Event/State First power RTC startup time 1000 applied...

  • Page 13: Reset Design Details

    If an external reset is desired, the signal must be either open collector or open drain without any form of pullup. Do not pull this line high with either a pullup or a driven logic one. When this line is pulled low, the JF2 will immediately drop into hibernate mode with some loss of data.

  • Page 14: Example Implementations

    JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 Example Implementations This section illustrates the implementations that meet the rules for the JF2. Telit recommends assessing the risks when making implementation decisions 3.1. Normal Operation Startup and Shutdown To start the JF2: Send a voltage pulse (tolerant to 3.6V) to the ON-OFF input.

  • Page 15: Updating The Firmware: Flash Module (Only)

    3. Apply main power if not already applied. 4. Pulse the ON-OFF signal to place the JF2 module into BOOT mode. 5. Run the software utility to re-flash the JF2 module. Clearing the entire flash memory is strongly recommended prior to programming.

  • Page 16: Updating Patch Code: Eeprom And Rom Modules With Host Memory

    JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 Updating Patch Code: EEPROM and ROM modules with Host Memory Modules with EEPROM and ROM-only designs using external Host memory support firmware patching. Firmware patches for the EEPROM module are stored inside the I2C serial EEPROM device.

  • Page 17: Rom2.2 Features

    SPI Flash Support SPI flash provides external storage for features such as patches, SGEE, CGEE, broadcast ephemeris data, and data logging. This feature is only supported by the JF2 ROM2.2 variant. 6.1.1. Hardware Interface The SPI flash is connected through the following four GPIO pins ...

  • Page 18: Main Serial Interface

    1vv0300985 Rev.4 2013-04-09 Main Serial Interface The JF2 has the capability to operate in serial UART mode, SPI mode or I2C mode depending upon how the JF2 GPIO6 and GPIO7 pins are strapped at power up. Either leave the pin floating, apply a 10K resistor to +1.8V (PU) or apply a 10K resistor to GND (PD).

  • Page 19: Uart Mode

    The GPIO6 pin should be pulled high through a 10K resistor to the 1.8 volt supply. The GPIO7 pin can be left open or pulled high. Upon power up, the JF2 will communicate using a standard asynchronous 8 bit protocol with messages appearing on the TX line, and commands and data being entered on the RX line.

  • Page 20: Spi Mode

    1vv0300985 Rev.4 2013-04-09 7.3. SPI Mode If both the GPIO6 and GPIO7 pins are left floating, the JF2 will power up in slave SPI mode, supporting both SPI and Microwire formats. In this mode, the four pins are defined below: Signal Name...

  • Page 21: Mems Sensor/Eeprom Interface

    FREESCALE part number MMA8450Q) can be used. The interrupt output of the accelerometer must be connected to GPIO4 of the JF2. Data for the approved magnetic sensor (Aichi Steel part number AIM304, 3.5 x 4.0mm 3V 3 axis magnetometer) is output in OSP message 72.

  • Page 22: Rf Front End Design

    GPS-200E, and the signal level typically goes higher as the satellites have higher elevation angles. The JF2 will display a reported C/No of 40 dB-Hz for a signal level of -130 dBm into the RF input. Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
  • Page 23 JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 Each GPS satellite presents its own signal to the JF2, and best performance is obtained when the signal levels are between -125 dBm and -117 dBm. These received signal levels are determined by ...

  • Page 24: Gps Antenna Polarization

    JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 9.2. GPS Antenna Polarization The GPS signal as broadcast is a right hand circularly polarized signal. The best antenna to receive the GPS signal is a right hand circularly (RHCP) polarized antenna. Remember that IS-GPS-200E specifies the receive power level with a linearly polarized antenna.

  • Page 25: System Noise Floor

    Thermal noise is -174 dBm/Hz at around room temperature. From this we can compute a system noise figure of 4 dB for the JF2. This noise figure consists of the loss of the pre-select SAW filter, the noise figure of the LNA as well as implementation losses within the digital signal processing unit.

  • Page 26: Implications Of The Pre-Select Saw Filter

    JF2. If a higher gain LNA is used, either a resistive Pi or T attenuator can be inserted after the LNA to bring the gain down to 14 dB or the JF2 can be switched into a low gain mode by issuing an OSP command to do so.

  • Page 27: Powering The External Lna (Active Antenna)

    DC voltage that is impressed upon the RF signal line. This voltage is not supplied by the JF2, but can be easily supplied by the host design. Two approaches can be used. The first is to use an inductor to tie directly to the RF trace. This inductor should be at self resonance at L1 (1.57542 GHz) and should have good Q for low...

  • Page 28: Rf Interference

    As mentioned earlier, the GPS signals are at -130 dBm and lower. If signal higher than this are presented to the receiver it can be overwhelmed. The JF2 can reject up to 8 CW in-band jamming signals, but would still be affected by non-CW signals.

  • Page 29: Reference Design

    Figure 2 – JF2 Reference Design (Flash, EEPROM, ROM2.0) – Active Antenna 10.1. Flash, EEPROM, ROM2.0 Reference Design Along with power and ground, the minimum number of signals required to operate the JF2 properly are four digital signals and one RF signal. 10.1.1.

  • Page 30: Serial Interface

     If the user wishes the JF2 to power up into the ON state and is willing to live with reduced power management options, then ON-OFF can be tied directly to SYSTEM- ON. In this case, GPIO8 should be pulled high with a pullup resistor to VDD_18.

  • Page 31: Rom2.2 9600Bps

    10.2. ROM2.2 9600bps The JF2 ROM2.2 9600bps variant does not support external EEPROM connection or MEMS connection. Note that if a SPI flash is connected, the baud rate defaults to 4800. Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.

  • Page 32: Firmware Configuration

    JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 Firmware Configuration The JF2 can be configured by means of firmware in order to fit better into the overall system. This section describes certain aspects of the receiver that can be configured. 11.1.

  • Page 33: Push-To-Fix

    If the JF2 is operated in TricklePower mode, a baud rate of at least 38400 is recommended. This reduces the time required for data output and allows the receiver to drop into the lowest power state for a longer average time.

  • Page 34: Mems Configuration

    Once the sensor interface has been configured and the sensors enabled, the sensor data will be output by the JF2 in OSP Message 72, Sub ID 1. Note that a data message is output for each sensor and can contain several sets of data from the given sensor.

  • Page 35: Mems Static Detection

    4MHz from the L1 frequency for jammers. Any number of jammers that occur outside of a +/-1MHz center band are removed by the JF2 with a 2MHz band pass filter. Up to eight jammers inside this center band are removed using a notch filter.

  • Page 36: 2-D Acquisition

    To accommodate applications for which these situations are a concern, a version of JF2 firmware is offered that requires a calculated altitude, i.e. a 3-D navigational solution, in order for the receiver to first enter navigation.

  • Page 37: Handling And Soldering

    020. This rating is assigned due to some of the components used within the JF2. The JF2 is supplied in trays or tape and reel and is hermetically sealed with desiccant and humidity indicator card. The JF2 parts must be placed and reflowed within 168 hours of first opening the hermetic seal provided the factory conditions are less than 30°C and less than...

  • Page 38: Esd

    020. The reflow profile must not exceed the profile given IPC/JEDEC J-STD-020 Table 5-2, “Classification Reflow Profiles”. Although IPC/JEDEC J-STD-020 allows for three reflows, the assembly process for the JF2 uses one of those profiles. Thus the JF2 is limited to two reflows.

  • Page 39: Pcb Layout Details

    1vv0300985 Rev.4 2013-04-09 PCB Layout Details The PCB footprint on the receiving board should match the JF2 pad design shown below. The solder mask opening is generally determined by the component geometry of other parts on the board and can be followed here.

  • Page 40: Document History

    JF2 Hardware User Guide 1vv0300985 Rev.4 2013-04-09 Document History Revision Date Changes 2011-01-19 First issue 2012-11-14 Made corrections for Figure 2 2012-11-29 Added ON_OFF notes in section 2.3 and update Figure 4 and 10.1 2013-03-19 Updated ON-OFF section and added ROM2.2 features...

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