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AMN11310 WHDI Transmitter Module Datasheet Version 0.4 Version 0.4 AMIMON Confidential...
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AMIMON to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from AMIMON under the patents or other intellectual property of AMIMON.
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Test Points and Jumpers 20.7.08 Fixed link to STMF datasheet p-12. Fixed pin id of WHDI connector p -25 Fixed recommended stack up table p- 23 Fixed power requirements p- 2 2.9.08 Change in FCC chapter Version 0.4 AMIMON Confidential...
Two-Wire Serial Bus Interface ....................... 12 3.3.2 Interrupts ............................13 3.3.3 WHDI Module Configuration ......................14 Reset and Wake-up Timer.......................... 14 Chapter 4, WHDI Connector Pins................17 Signals ................................. 17 Connector Schematics..........................18 Pin List ................................. 19 Version 0.4 AMIMON Confidential...
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Power and Ground ......................... 24 RF Design Recommendation........................24 6.2.1 RF Components ..........................24 6.2.2 Power Management ........................24 Test Points and Jumpers........................... 25 Chapter 7, Mechanical Dimensions ................27 RF Shield Frame and Cover........................29 Version 0.4 AMIMON Confidential...
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Table 10: Absolute Maximum Ratings over Operating Case Temperature Range..........21 Table 11: Recommended Operating Conditions ..................... 21 Table 12: Electrical Characteristics over Recommended Range of Supply Voltage and Operating Conditions ..21 Table 13: Digital Layout Recommendation ......................23 Version 0.4 AMIMON Confidential...
The WHDI system transmits uncompressed video and audio streams wirelessly and thus simplifies and eliminates system issues such as lip-sync, large buffers and other burdens like retransmissions or error propagation. Features Uncompressed and uncompromised HD video quality, using AMIMON's baseband chipsets: • AMN2110: WHDI Baseband Transmitter...
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(1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Any changes or modifications not expressly approved by Amimon for compliance could void the user's authority to operate the equipment.
Chapter 2 Overview The AMN11310 WHDI Video Source Unit (VSU) is designed to modulate and transmit downstream video and audio content over the wireless medium and receive a control channel over the wireless upstream. The modulation uses 18MHz bandwidth and is carried over the 5GHz unlicensed band. Figure 1 displays a block diagram of the AMN11310.
• AMN2110 WHDI Baseband Transmitter The AMN2110 WHDI baseband transmitter chip is the heart of the AMN11310 WHDI transmitter module. The AMN2110 interfaces the A/V source through the WHDI connector, and is controlled on board by the MAC uC. WHDI...
This clock is named DIG_CLK. The control to the output buffer is named Clk40M_OE. 2.6.3 10Mhz Micro Controller Clock The DIG_CLK (40MHz) clock is divided by four by the AMN2110 and generates 10MHz that drives the STM32F Version 0.4 AMIMON Confidential...
The antenna switching switch controls two input options: reception from on board printed antenna or SPIFA (standing antenna) for uplink channel. This switch is controlled by two general purpose pins of the STM32F UC: GPIO PB6 pin#58 and PB7 pin#59. Version 0.4 AMIMON Confidential...
DATA Enable (DE) Generator The AMN2110 includes logic to construct the DE signal from the incoming HSYNC, VSYNC and clock. Registers are programmed to enable the DE signal to define the size of the active display region. Version 0.4 AMIMON Confidential...
TDCKFREQ DCLK frequency 13.5 TDCKDUTY DCLK duty cycle TDCKSUR Setup time to DCLK rising edge TDCKHDR Hold time to DCLK rising edge TDCKSUF Setup time to DCLK falling edge TDCKHDF Hold time to DCLK falling edge Version 0.4 AMIMON Confidential...
The AMN11310 can accept digital audio from either SPDIF or I2S inputs. The AMN11310 supports two channel audio sampling frequencies of up to 48KHz and of up to 32 bits per sample (For I S – only 24 bits are supported). Version 0.4 AMIMON Confidential...
Table 4: I2S Audio Interface Timing Requirements Symbol Parameter Units TSCKCYC SCK period TSCKFREQ SCK frequency 1.024 3.072 TSCKDUTY SCK duty cycle TDCKSETUP Setup time to SCK rising edge TDCKHOLD Hold time to SCK rising edge Version 0.4 AMIMON Confidential...
The AMN11310 does not require the SPDIF clock. The clock is produced internally by sampling the SPDIF data input at a high clock rate and processing it. Table 5: Audio Interface Timing Requirements Symbol Parameter Condition Units TSPCYC SPDIF data sampling rate TSPFREQ SPDIF data sampling freq 2.048 6.144 Version 0.4 AMIMON Confidential...
The MAC device address may be altered by two jumpers on VDU/VSU board. Table 6: Device Addresses Device Address MAC uC 0x62 or 0x82 or 0x90 or 0x70 (Board configuration dependant) Alternatively, the device address can be set in the MAC SW in advance. Version 0.4 AMIMON Confidential...
There is one interrupt connected to the WHDI connector. The interrupt source is the AMN2110 MAC uC. For details about the interrupt, please refer to the Programmer's User Guide. The interrupt active polarity is set in SW or by configuration resistors on board – see 3.3.3. Version 0.4 AMIMON Confidential...
3.3.3 WHDI Module Configuration In order to distinguish between boards and by the SW, there is an on board id that can be read by the STM32F. WHDI_MODULE_ID (Details) Comments Amimon Project Tx="0", Interrupt Polarity: I2C Address: "00"=0x62, MODULE_ID Part Number Rx="1"...
ST,RST STM32F completes the internal initialization Time from assertion of the HW/SW reset until the INIT AMN2110 completes the internal initialization The following figure specifies the reset schema and related signals - Figure 11: Reset Mechanism Version 0.4 AMIMON Confidential...
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Interfaces Version 0.4 AMIMON Confidential...
RESET TBD[5:4] TBD4, TBD5 are reserved in AMN11310, as an option for RS232 connection to STM32F UART2. 3.3V Power Power 300 mA maximum rating per pin Ground Power Power † Data in this table is preliminary. Version 0.4 AMIMON Confidential...
Off-state output current = DV or 0 V µ A ± 20 Module supply 1800 = Max., Video Clock = 74.25 MHz, DVDD with activity on all I/O terminals and transmitting in maximum power. Input capacitance Output capacitance Version 0.4 AMIMON Confidential...
Power / Ground Space Ground Space Print Side (PS) 1-1.5 Trace Width - 5. mil, Separation between differential lines – 6 mil, differential impedance - 107 OHM. Board Thickness 1.15 MM +\- 10% Material FR4 HITG Version 0.4 AMIMON Confidential...
RF Design Recommendation 6.2.1 RF Components All passive components must have compatible performance with components used in the Amimon reference design. 6.2.2 Power Management The RF power rail 3.3V_RAIL is separated from the digital power rail 3.3 with ferrite bead.
Mechanical Dimensions Chapter 7 Mechanical Dimensions The following shows the mechanical dimensions for the AMN11310: Figure 13: Mechanical Dimensions Top View Version 0.4 AMIMON Confidential...
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