Related Manuals for AMIMON AMN12310 WHDI
Summary of Contents for AMIMON AMN12310 WHDI
- Page 1 AMN12310 WHDI Receiver Module Datasheet Version 0.5 Version 0.5 AMIMON Confidential...
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Page 2: Important Notice
AMIMON to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from AMIMON under the patents or other intellectual property of AMIMON. -
Page 3: Revision History
Test Points and Jumpers 20.7.08 Fixed link to STMF datasheet p-18. Fixed Table 1: Rx WHDI Connector Pin List Fixed recommended stack up table p- 29 03.08.08 Add section MCLK Specifications 2.9.08 Change in FCC chapter Version 0.5 AMIMON Confidential... -
Page 4: Table Of Contents
10Mhz Micro Controller Clock ......................13 CY22150 External Video PLL ........................14 Chapter 3 ......................15 Interfaces ......................15 Video Data Input and Conversions.......................15 Video Interface Output Timing Diagram ....................16 3.2.1 Timing Requirements ........................16 Audio Data Capture ..........................17 Version 0.5 AMIMON Confidential... - Page 5 6.1.4 Power and Ground .......................... 33 RF Design Recommendation ........................33 6.2.1 RF Components ..........................33 6.2.2 Power Management ........................33 Test Points and Jumpers ........................34 Chapter 7 ......................36 Mechanical Dimensions ..................36 RF Shield frame and cover........................38 Version 0.5 AMIMON Confidential...
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Page 6: List Of Figures
Table 8: Reset Timing Requirements........................24 Table 9: WHDI Connector Signals .......................... 26 Table 10: Rx WHDI Connector Pin List ........................28 Table 11: Absolute Maximum Ratings over Operating Case Temperature Range..........30 Table 12: Recommended Operating Conditions ..................... 30 Version 0.5 AMIMON Confidential... - Page 7 List of Tables Table 13: Electrical Characteristics over Recommended Range of Supply Voltage and Operating Conditions............................30 Table 14: Digital Layout Recommendation ......................32 Version 0.5 AMIMON Confidential...
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Page 8: Chapter 1
Features Uncompressed and uncompromised HD video quality, using AMIMON's baseband chipsets: • AMN2210: WHDITM Baseband Receiver AMN3210: WHDITM RFIC Receiver WHDI –... - Page 9 (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Any changes or modifications not expressly approved by Amimon for compliance could void the user's authority to operate the equipment.
- Page 10 Introduction Caution: The module should be positioned so that personnel in the area for prolonged periods may safely • remain at least 20 cm (8 in) in an uncontrolled environment from the module. Version 0.5 AMIMON Confidential...
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Page 11: Chapter 2
Chapter 2 Overview The AMN12310 WHDI Video Display Unit (VDU) is designed to be at the receiver end of the WHDI downstream. The AMN12310 receives wireless downstream transmission, demodulates it and regenerates the video, audio and control content transmitted by the AMN11310 WHDI transmitter. The receiver works at the 5GHz unlicensed band. -
Page 12: Amn2210 Whdi Baseband Receiver
• AMN2210 WHDI Baseband Receiver The AMN2210 WHDI baseband receiver chip is the heart of the AMN12310 WHDI Receiver module. The AMN2210 interfaces the A/V source through the WHDI connector, and is controlled on board by the MAC uC. WHDI... -
Page 13: Tm 5Ghz Transceiver
This clock is named DIG_CLK. The control to the output buffer is named Clk40M_OE. 2.6.3 10Mhz Micro Controller Clock The DIG_CLK (40MHz) clock is divided by four by the AMN2210 and generates 10MHz that drives the STM32F Version 0.5 AMIMON Confidential... -
Page 14: Cy22150 External Video Pll
10 MHz), which is generated inside the AMN2210 according to the video parameters. The PLL multiplies the clock to the desired speed dictated by the incoming video format (for example: 74.25Mhz for 720p or 1080i). Version 0.5 AMIMON Confidential... -
Page 15: Chapter 3
The receiver can output either RGB or YCbCr color space. For more details, you may refer to the MAC registers in the programmer's reference guide. Color Range Limiter The YCbCr data range can be limited to 16-235. Version 0.5 AMIMON Confidential... -
Page 16: Video Interface Output Timing Diagram
DCLK frequency TDCKDUTY DCLK duty cycle TDCKPDR Propagation delay after DCLK rising edge TDCKPDF Propagation delay after DCLK falling edge * It is possible to support lower clock frequency using an external PLL for video clock generation. Version 0.5 AMIMON Confidential... -
Page 17: Audio Data Capture
No constraints exist for a coherent video and audio clock, where coherent means that the audio and the video clock must have been created from the same clock source. The AMN12310 supports two-channel audio-sampling frequencies of up to 48 KHz, 32 bits per sample. Version 0.5 AMIMON Confidential... -
Page 18: I 2 S Bus Specification
32 bits. 3.3.1.1 MUTE The AMN12310 has an error detection mechanism. It outputs a high MUTE signal in case of bad audio reception (bad frames). Version 0.5 AMIMON Confidential... -
Page 19: Figure 6: I 2 S Output Timings
MCLK frequency is 256 times the sampling frequency of the audio signal. For example, if the audio sampling frequency is 48 KHz, the MCLK frequency will be 12.288 MHz. The following table provides the specification of the MCLK – Version 0.5 AMIMON Confidential... -
Page 20: Table 6: Mclk Timing
** The maximum frequency is obtained by using the minimum audio sampling frequency 48 KHz and the minimum clock rate multiplication of 256. *** The cycle-to-cycle jitter is based on the system clock of the AMN2210, which is 200 MHz. Version 0.5 AMIMON Confidential... -
Page 21: Management Buses And Connectors
The MAC device address may be altered by two jumpers on VDU/VSU board. Table 7: Device Addresses Device Address MAC uC 0x62 or 0x82 or 0x90 or 0x70 (Board configuration dependant) Alternatively, the device address can be set in the MAC SW in advance. Version 0.5 AMIMON Confidential... -
Page 22: Interrupts
There is one interrupt connected to the WHDI connector. The interrupt source is the AMN2210 MAC uC. For details about the interrupt, please refer to the programmer's user guide. . The interrupt active polarity is set in SW or by configuration resistors on board – see 3.4.3. Version 0.5 AMIMON Confidential... -
Page 23: Whdi Module Configuration
Interfaces 3.4.3 WHDI Module Configuration In order to distinguish between boards and by the SW, there is an on board ID that can be read by the STM32F. WHDI_MODULE_ID (Details) Comments Amimon Project Tx="0", Interrupt Polarity: I2C Address: "00"=0x62, MODULE_ID Part Number Rx="1"... -
Page 24: Figure 11: Reset Mechanism
ST,RST STM32F completes the internal initialization Time from assertion of the HW/SW reset until the INIT AMN2210 completes the internal initialization The following figure specifies the reset schema and related signals - Figure 11: Reset Mechanism Version 0.5 AMIMON Confidential... - Page 25 Interfaces Version 0.5 AMIMON Confidential...
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Page 26: Chapter 4
TBD[5:4] TBD4, TBD5, are reserved in, AMN12310 as an option for RS232 connection to STM32F UART2. 3.3V Power Power 300 mA maximum rating per Ground Power Power Version 0.5 AMIMON Confidential... -
Page 27: Connector Schematics
WHDI Connector Pins Connector Schematics Figure 12: WHDI Connector Version 0.5 AMIMON Confidential... -
Page 28: Pin List
3.3V WHDI_D14 WHDI_D15 WHDI_D13 WHDI_DCLK WHDI_D11 WHDI_D9 WHDI_D12 WHDI_D7 WHDI_D10 WHDI_D5 WHDI_D8 WHDI_D3 WHDI_D6 WHDI_D1 WHDI_TBD4 WHDI_D4 WHDI_D0 WHDI_TBD5 WHDI_D2 WHDI_DE WHD_RESET_ WHDI_SCL WHDI_H_SYNC WHDI_V_SYNC WHDI_INT WHDI_SDA WHDI_MCLK WHDI_SPDIF MUTE WHDI_I2S_D0 (TBD6) WHDI_D28 WHDI_D29 WHDI_LRCLK WHDI_SCLK Version 0.5 AMIMON Confidential... - Page 29 WHDI Connector Pins Version 0.5 AMIMON Confidential...
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Page 30: Chapter 5
± 20 µ A Off-state output current = DV or 0 V µ A ± 20 Module supply = Max., Video Clock = 74.25 MHz, 1500 DVDD with activity on all I/O terminals Input capacitance Output capacitance Version 0.5 AMIMON Confidential... - Page 31 Electrical Specifications Version 0.5 AMIMON Confidential...
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Page 32: Chapter 6
Space Power / Ground Space Ground Space Print Side (PS) 1-1.5 Trace Width - 5mil, Separation between differential lines – 6 mil, differential impedance - 107 OHM. Board Thickness 1.15 MM +/- 10% Material FR4 HITG Version 0.5 AMIMON Confidential... -
Page 33: General Guidelines
RF Design Recommendation 6.2.1 RF Components All passive components must have compatible performance with components used in the Amimon reference design. 6.2.2 Power Management The RF power rail 3.3V_RAIL is separated from the digital power rail 3.3 with ferrite bead. -
Page 34: Test Points And Jumpers
UC JTAG TP22 JP1 pin 1-2 JUMPER MAC_TXD TP23 3.3V JP1 pin 2-3 JUMPER ALB_TXD TP24 3.3V JP2 pin 1-2 JUMPER MAC_RXD TP25 MAC_RST JP2 pin 2-3 JUMPER ALB_RXD TP26 MAC_TMS JUMPER BOOT0 TP27 3.3V SWITCH RF_TEST_SW Version 0.5 AMIMON Confidential... - Page 35 Design Guidelines Version 0.5 AMIMON Confidential...
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Page 36: Chapter 7
Mechanical Dimensions Chapter 7 Mechanical Dimensions The following shows the mechanical dimensions for the AMN12310: Figure 13: Mechanical Dimensions Top View Version 0.5 AMIMON Confidential... -
Page 37: Figure 14: Mechanical Dimensions Bottom View
Mechanical Dimensions Figure 14: Mechanical Dimensions Bottom View Version 0.5 AMIMON Confidential... -
Page 38: Rf Shield Frame And Cover
Mechanical Dimensions RF Shield frame and cover Figure 15: RF-Shield Frame Figure 16: RF-Shield Cover Version 0.5 AMIMON Confidential... - Page 39 Mechanical Dimensions Version 0.5 AMIMON Confidential...
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