3 Local Space Addressing 3.1 XR17D158 Local Space Configuration XR17D158 PCI Base Size Port Endian Description Address Space Width Mode (Byte) Mapping (Offset in PCI (Bit) Configuration Space) 3.2 Device Configuration Space PCI Base Address: XR17D158 PCI Base Address 0 (Offset 0x10 in PCI Configuration Space).
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3.2.1 UART Register Sets UART Register Set Register Set Offset Offset Address Description Access Data Width...
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The address for a UART Channel Configuration Register x in a UART Register Set for channel y PCI Base Address 0 (PCI Base Address for the UART Register Space) + UART Register Set Offset for channel y + Register Offset for register x...
5.4 RS485/RS422 Configuration Examples 5.4.1 RS422 Multidrop RS485 HDPLX RENA RTERM TTERM FCTR[5] 5.4.2 RS422 Full Duplex Point to Point RS485 HDPLX RENA RTERM TTERM FCTR[5] 5.4.3 RS485 Full Duplex Point to Point RS485 HDPLX RENA RTERM TTERM FCTR[5]...
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5.4.4 RS485 Half Duplex Point to Point RS485 HDPLX RENA RTERM TTERM FCTR[5] 5.4.5 RS485 Full Duplex Multi-point Master RS485 HDPLX RENA RTERM TTERM FCTR[5] Slave RS485 HDPLX RENA RTERM TTERM FCTR[5]...
I/O connector and P14 back I/O connector at the same time. Please note that on the TPMC465 the P14 back I/O connector is always populated and connected to on board logic. Do not use these modules on carrier boards where P14/J14 is reserved for other system signals but PMC I/O.
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