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Summary of Contents for Tews Technologies TPCE863
- Page 1 TPCE863 4 Channel High Speed Sync/Async Serial Interface Version 1.0 User Manual Issue 1.0.1 August 2014 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek, Germany Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19 e-mail: info@tews.com www.tews.com...
- Page 2 However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
- Page 3 Issue Description Date 1.0.0 Initial Issue September 2012 1.0.1 General Revision August 2014 TPCE863 User Manual Issue 1.0.1 Page 3 of 72...
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Page 4: Table Of Contents
CHiLTDA – Channel i Last Transmit Descriptor Address Register ........34 5.5.18 VR – Version Register ......................34 5.5.19 ISPR – In-System-Programming Register ................34 5.5.20 GCTLR – Global Control Register ..................35 TPCE863 User Manual Issue 1.0.1 Page 4 of 72... - Page 5 Clock Recovery (DPLL) ........................ 66 CONFIGURATION HINTS ................... 67 Big / Little Endian ..........................67 Configuration EEPROM ........................67 Additional Termination Resistors ....................68 Transmit & Receive Clock Polarity ....................69 TPCE863 User Manual Issue 1.0.1 Page 5 of 72...
- Page 6 MODULE MANAGEMENT ..................70 On Board LEDs ..........................70 10 PIN ASSIGNMENT – I/O CONNECTOR ..............71 10.1 Front Panel I/O Connector ......................71 TPCE863 User Manual Issue 1.0.1 Page 6 of 72...
- Page 7 FIGURE 7-4 : FM0 AND FM1 DATA ENCODING................... 65 FIGURE 7-5 : MANCHESTER DATA ENCODING ..................65 FIGURE 8-1 : TRANSMIT & RECEIVE CLOCK POLARITY ................69 FIGURE 10-1 : FRONT PANEL I/O CONNECTOR NUMBERING ..............71 TPCE863 User Manual Issue 1.0.1 Page 7 of 72...
- Page 8 TABLE 5-32: INTERRUPT STATUS REGISTER.................... 46 TABLE 5-33: ADDITIONAL CONFIGURATION REGISTER ................48 TABLE 5-34: PHYSICAL INTERFACE MODE SELECTION ................48 TABLE 6-1 : TRANSMIT DESCRIPTOR ......................50 TABLE 6-2 : RECEIVE DESCRIPTOR ......................52 TPCE863 User Manual Issue 1.0.1 Page 8 of 72...
- Page 9 TABLE 7-1 : PROTOCOL MODES ......................... 60 TABLE 8-1 : CONFIGURATION EEPROM DATA ..................68 TABLE 9-1 : ON BOARD LEDS ........................70 TABLE 10-1 : FRONT I/O PIN ASSIGNMENT ....................72 TPCE863 User Manual Issue 1.0.1 Page 9 of 72...
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Page 10: Product Description
1 Product Description The TPCE863 is a standard height, half length PCI Express 1.1 compliant module with four high speed serial data communication channels. The serial communication controller is implemented in FPGA logic, along with the bus master capable PCI interface, guaranteeing long term availability and having the option to implement additional functions in the future. -
Page 11: Technical Specification
If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation. Humidity 5 – 95 % non-condensing Weight TPCE863-10R: 86 g Table 2-1 : Technical Specification TPCE863 User Manual Issue 1.0.1 Page 11 of 72... -
Page 12: Handling And Operation Instructions
3 Handling and Operation Instructions ESD Protection The TPCE863 is sensitive to Electrostatic Discharge (ESD). Packing, unpacking and all other handling of the TPCE863 has to be done in an ESD/EOS protected Area. TPCE863 User Manual Issue 1.0.1 Page 12 of 72... -
Page 13: On Board Devices
PCIe interface and the on board PCI bus (i.e. the FPGA). PI7C9X111SL PCIe/PCI Bridge The PI7C9X111SL is a PCI Express to PCI reversible bridge. On the TPCE863 the PI7C9X111SL is used in transparent, forward mode only. 4.2.1 PI7C9X111SL Register Map... -
Page 14: Pci Express Configuration Space Register Mapping
0x38 PCI Base Address for Expansion ROM 00000000 0x3C Bridge Control Internal PCI Internal PCI 0000 01 00 Interrupt Wire Interrupt Line Table 4-2 : PI7C9X111SL PCI-Compatible Configuration (Type 1) Registers TPCE863 User Manual Issue 1.0.1 Page 14 of 72... -
Page 15: Pci-Compatible Extended Capability Registers
0xF4 Message Signaled Interrupts Address 0000 0000 0xF8 Message Signaled Interrupts Upper Address 0000 0000 0xFC Reserved Message Signaled Interrupts Data 0000 0000 Table 4-3 : PI7C9X111SL PCI-Compatible Extended Capability Registers TPCE863 User Manual Issue 1.0.1 Page 15 of 72... -
Page 16: Configuration Eeprom
The FPGA implements a set of control & status registers as a PCI target, accessible in the PCI memory space. The FPGA also implements a PCI DMA/Master engine used for the data transfers to and from host/system memory. The FPGA configures from a serial Flash after power-up. TPCE863 User Manual Issue 1.0.1 Page 16 of 72... -
Page 17: Pci Configuration Space
4.3.1 PCI Configuration Space The SCC FPGA is assigned PCI device number 0 on the TPCE863 embedded PCI bus. PCI Configuration Space Header Offset Device ID Vendor ID 0x00 (TPCE863: 0x735F) (TEWS Technologies 0x1498) 0x04 Status Command Class Code 0x08... -
Page 18: Address Map
5 Address Map Register Space The Register Space is accessible in the PCI Memory Space of the TPCE863 embedded PCI bus. The Register Space Base address is found at PCI BAR0 (Offset 0x10) in the PCI Configuration Space of the... -
Page 19: Global Register Map
CH3CFG Channel 3 Configuration Register 0x0078 CH3BRDA Channel 3 Base Rx Descr. Address 0x007C CH3BTDA Channel 3 Base Tx Descr. Address 0x0080...0x0097 reserved 0x0098 CH0FRDA Channel 0 First Rx Descr. Address TPCE863 User Manual Issue 1.0.1 Page 19 of 72... -
Page 20: Scc Register Map
Register Space PCI Base Address + SCC Channel Offset + SCC Register Offset Register Space PCI Base Address: PCI Base Address 0 (Offset 0x10 in the PCI Configuration Space of the FPGA PCI Device) TPCE863 User Manual Issue 1.0.1 Page 20 of 72... -
Page 21: Table 5-4 : Scc Register Map
Baud Rate Register 0x30…0x47 reserved 0x48 Termination Character Register 0x4C…0x53 reserved 0x54 Interrupt Mask Register 0x58 Interrupt Status Register 0x5C Additional Configuration Register 0x60...0x7F reserved Table 5-4 : SCC Register Map TPCE863 User Manual Issue 1.0.1 Page 21 of 72... -
Page 22: Global Registers
CFGIQSCC2RX Configure Interrupt Queue SCC2 Receive (see above) CFGIQSCC1RX Configure Interrupt Queue SCC1 Receive (see above) CFGIQSCC0RX Configure Interrupt Queue SCC0 Receive (see above) TPCE863 User Manual Issue 1.0.1 Page 22 of 72... - Page 23 Upon action request, the DMA (interrupt) controller will evaluate the configuration interrupt queue base address and length registers which must have been programmed by software before. 20:14 Reserved (0 for reads) TPCE863 User Manual Issue 1.0.1 Page 23 of 72...
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Page 24: Table 5-5 : Global Command Register
Self-clearing command bit. '0': No action request '1': Action request Validates GCMDR CFGIQSCCiRX, CFGIQSCCiTX, CFGIQCFG register bits and CHiCFG RDR, RDT, IDR, IDT register bits. Table 5-5 : Global Command Register TPCE863 User Manual Issue 1.0.1 Page 24 of 72... -
Page 25: Gstar - Global Status Register
’0’: No new interrupt vector was transferred into the corresponding queue. ’1’: At least one new interrupt vector was transferred into the corresponding queue. 23:22 Reserved (0 for reads) TPCE863 User Manual Issue 1.0.1 Page 25 of 72... -
Page 26: Gmode - Global Mode Register
’HOLD’ bit in each receive/transmit descriptor. ’1’ Last Receive/Transmit Descriptor Address mode. The descriptor chain end condition is controlled via registers LRDA/LTDA. Table 5-7 : Global Mode Register TPCE863 User Manual Issue 1.0.1 Page 26 of 72... -
Page 27: Iqlenr0 - Interrupt Queue Length Register 0
23:20 IQCFGLEN Interrupt Queue Configuration Length Queue Length = (1 + ’IQCFGLEN’) * 32 DWORDS, ’IQCFGLEN’ = 0...15 19:0 Reserved (0 for reads) Table 5-9 : Interrupt Queue Length Register 1 TPCE863 User Manual Issue 1.0.1 Page 27 of 72... -
Page 28: Iqsccirxbar - Interrupt Queue Scci Receiver Base Address Register
5.5.7 IQSCCiTXBAR – Interrupt Queue SCCi Transmitter Base Address Register (i=0...3) (0x0024, 0x0028, 0x002C, 0x0030) Symbol Description Access Reset Value 31:2 IQSCCiTXBAR PCI Base Address of Transmit Interrupt Queue Table 5-11: IQSCCiTXBAR Register TPCE863 User Manual Issue 1.0.1 Page 28 of 72... -
Page 29: Fifocr4 - Fifo Control Register 4
DMAC to transfer all data immediately. This may be useful for not frame oriented data transmission, e.g. in ASYNC protocol mode. Table 5-12 : FIFO Control Register 4 TPCE863 User Manual Issue 1.0.1 Page 29 of 72... -
Page 30: Iqcfgbar - Interrupt Queue Configuration Base Address Register
TFSIZE0 Main Transmit-FIFO Size (Depth) Channel 0 Main Transmit-FIFO Size (Depth) is 2 power (TFSIZEi + 2) FIFO Size (Depth) in TFSIZEi DWords (4 Bytes) Table 5-14: FIFO Control Register 1 TPCE863 User Manual Issue 1.0.1 Page 30 of 72... -
Page 31: Chicfg - Channel I Configuration Register
(i=3..0): ’0’: ERR interrupt generation is enabled for the dedicated DMA transmit channel. ’1’: ERR interrupt generation is disabled for the dedicated DMA transmit channel. Reserved (0 for reads) TPCE863 User Manual Issue 1.0.1 Page 31 of 72... -
Page 32: Table 5-15: Chicfg Register
Note: To avoid unexpected DMA controller behavior, it is recommended to apply ’IDT’ command only, if the specific DMA channel is in reset state. 18:0 Reserved (0 for reads) Table 5-15: CHiCFG Register TPCE863 User Manual Issue 1.0.1 Page 32 of 72... -
Page 33: Chibrda - Channel I Base Receive Descriptor Address Register
5.5.16 CHiLRDA – Channel i Last Receive Descriptor Address Register (i=0...3) (0x00C8, 0x00CC, 0x00D0, 0x00D4) Symbol Description Access Reset Value 31:2 CHiLRDA PCI Base Address of Last Receive Descriptor Table 5-20: CHiLRDA Register TPCE863 User Manual Issue 1.0.1 Page 33 of 72... -
Page 34: Chiltda - Channel I Last Transmit Descriptor Address Register
5.5.19 ISPR – In-System-Programming Register (0x00F4) This register is reserved for (factory) reprogramming of the FPGA configuration flash. No write accesses shall be done to this address, as permanent damage may occur. TPCE863 User Manual Issue 1.0.1 Page 34 of 72... -
Page 35: Gctlr - Global Control Register
LRST Local Reset Self-clearing command bit. The complete local part of the device is reset. Only the registers in the PCI configuration space keep their values. Table 5-23: Global Control Register TPCE863 User Manual Issue 1.0.1 Page 35 of 72... -
Page 36: Scc Channel Specific Registers
Recommended after changes in protocol configuration (switching between the protocol engines or sub- modes of HDLC). Note: A receive clock must be present. 15:0 Reserved (0 for reads) Table 5-24: Command Register TPCE863 User Manual Issue 1.0.1 Page 36 of 72... -
Page 37: Star - Status Register
DPLL is synchronized. ’1’ DPLL is asynchronous (re-synchronization process is started automatically). 18:1 Reserved (0 for reads) DSR3 Data Set Ready Channel 3 (Only on channel 3!) Table 5-25: Status Register TPCE863 User Manual Issue 1.0.1 Page 37 of 72... -
Page 38: Ccr0 - Channel Configuration Register 0
Transmitter/Receiver Clock Rate is Data Bit Rate x16. Bits are sampled 16 times. The result is determined by a majority decision of 3 samples around the bit center. NRZ encoding has to be selected. Reserved (0 for reads) TPCE863 User Manual Issue 1.0.1 Page 38 of 72... -
Page 39: Ccr1 -Configuration Register 1
’1’: Transmitter is always enabled. Note: In ASYNC mode the current byte is completely sent, even if CTS# becomes deasserted during transmission. 17:16 Reserved (0 for reads) TPCE863 User Manual Issue 1.0.1 Page 39 of 72... -
Page 40: Table 5-27: Channel Configuration Register 1
CRC-32 Polynom used is x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 Table 5-27: Channel Configuration Register 1 TPCE863 User Manual Issue 1.0.1 Page 40 of 72... -
Page 41: Ccr2 - Channel Configuration Register 2
The receiver does not expect a CRC. Note: A received checksum (2 or 4 bytes) is always forwarded to the receive buffer as data. Reserved (0 for reads) (hdlc) Reserved (0 for reads) TPCE863 User Manual Issue 1.0.1 Page 41 of 72... -
Page 42: Table 5-28: Channel Configuration Register 2
Transmit CRC Checking Mode (hdlc) (hdlc) ’0’: The transmit checksum (2 or 4 bytes) is generated and appended to the transmit data. ’1’: The transmit checksum is not generated. Table 5-28: Channel Configuration Register 2 TPCE863 User Manual Issue 1.0.1 Page 42 of 72... -
Page 43: Brr - Baud Rate Register
14:8 Reserved (0 for reads) Termination Character (async./isochr.) Defines the termination character which is monitored on the receive data stream if enabled via bit ’TCDE’. Table 5-30: Termination Character Register TPCE863 User Manual Issue 1.0.1 Page 43 of 72... -
Page 44: Imr - Interrupt Mask Register
(hdlc) PLLA CDSC Table 5-31: Interrupt Mask Register Unused interrupts shall be masked to avoid unwanted behavior. Especially CSC and CDSC should be masked if CTS and CD inputs are unconnected. TPCE863 User Manual Issue 1.0.1 Page 44 of 72... -
Page 45: Isr - Interrupt Status Register
It is set to ’1’, if a character with wrong parity has been received. If enabled via bit ’RFDF’, this error status is additionally stored in the receive status byte generated for each receive character. TPCE863 User Manual Issue 1.0.1 Page 45 of 72... -
Page 46: Table 5-32: Interrupt Status Register
If CCR0.VIS is set to ‘1’ then masked interrupt status bits will be visible in the ISR. To clear these interrupt flags, the host CPU must write ‘1’ to the corresponding ISR bit. TPCE863 User Manual Issue 1.0.1 Page 46 of 72... -
Page 47: Acr - Additional Configuration Register
‘0’: No inverting of TxC (the controller generates transmit data bits with the rising TxC edge) ‘1’: TxC is inverted (the controller generates transmit data bits with the falling TxC edge) TPCE863 User Manual Issue 1.0.1 Page 47 of 72... -
Page 48: Table 5-33: Additional Configuration Register
TxD,TxC,RxD,RxC,RTS,CTS,CD: V.11 EIA-530 TxD,TxC,RxD,RxC,RTS,CTS,CD: V.11 X.21 TxD,TxC,RxD,RxC,RTS,CTS,CD: V.11 V.35 TxD,TxC,RxD,RxC: V.35 / RTS,CTS,CD: V.28 EIA-449/V.36 TxD,TxC,RxD,RxC,RTS,CTS,CD: V.11 V.28/EIA-232 TxD,TxC,RxD,RxC,RTS,CTS,CD: V.28 TxD,TxC,RxD,RxC,RTS,CTS,CD: Z No Cable (high impedance) Table 5-34: Physical Interface Mode Selection TPCE863 User Manual Issue 1.0.1 Page 48 of 72... -
Page 49: Functional Description
Each descriptor contains a ’next descriptor address’ field to implement the linked list. Because the DMA controller cannot distinguish between valid and invalid addresses, a ’Hold’ mechanism is implemented to prevent the DMA controller from branching to invalid memory locations. TPCE863 User Manual Issue 1.0.1 Page 49 of 72... -
Page 50: Dmac Transmit Descriptor Lists
(HDLC) or the end of data block (ASYNC). When transferring the last data from this transmit data section into the internal FIFO the DMAC marks this data with a ’frame end / block end’ indication bit. TPCE863 User Manual Issue 1.0.1 Page 50 of 72... - Page 51 In this case the value in the BTDA register is used as a pointer for the next transmit descriptor. The descriptor start address must be DWORD aligned. TPCE863 User Manual Issue 1.0.1 Page 51 of 72...
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Page 52: Dmac Receive Descriptor Lists
Transmit Data Pointer: This 32-bit pointer contains the start address of the transmit data section for a transmit descriptor. Although the TPCE863 works long word oriented, it is possible to begin transmit data section at byte addresses. C: Complete Bit This bit is set by the DMAC if •... - Page 53 When both addresses differ, it branches to the next receive descriptor. Otherwise the corresponding DMAC receive channel is deactivated as long as the host CPU does not write a new value to the LRDA register or provides an action request with ’IDR’ command. TPCE863 User Manual Issue 1.0.1 Page 53 of 72...
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Page 54: Receive Data Section Status Byte (Hdlc Mode)
Table 6-4 : Receive Data Section Status Byte (HDLC) The contents of the RSTA byte relate to the received HDLC frame and are generated when end-of-frame is recognized at the serial receive interface. TPCE863 User Manual Issue 1.0.1 Page 54 of 72... -
Page 55: Receive Data Section Status Byte (Async Modes)
DMAC are transferred to the configuration queue IQCFG. The internal blocks provide mask registers for suppressing interrupt indications. Masked interrupts will neither generate an interrupt vector nor an INTA signal or GSTAR indication. TPCE863 User Manual Issue 1.0.1 Page 55 of 72... -
Page 56: Dma Controller Initiated Interrupts
FI and HI interrupt indications caused by one descriptor will be generated into one interrupt vector with ’HI’ and ’FI’ bit set. TPCE863 User Manual Issue 1.0.1 Page 56 of 72... -
Page 57: Interrupt Vector Description
Transmit Channel 0 Interrupt Vector (IQSCC0TX) Transmit Channel 1 Interrupt Vector (IQSCC1TX) Transmit Channel 2 Interrupt Vector (IQSCC2TX) Transmit Channel 3 Interrupt Vector (IQSCC3TX) Table 6-8 : DMA Interrupt Vector Source-IDs TPCE863 User Manual Issue 1.0.1 Page 57 of 72... - Page 58 Issued if a transmit descriptor contains a hold condition but FE=’0’ or if the last descriptor had NO=0 and FE=’0’. ERR=’0’ No Error (ERR) interrupt is indicated by this vector. ERR=’1’ An Error (ERR) interrupt is indicated by this vector. TPCE863 User Manual Issue 1.0.1 Page 58 of 72...
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Page 59: Scc Interrupt Vector
Table 6-10: SCC Interrupt Vector Source-IDs Bit field [18:0] of the SCC interrupt vector is a copy of the SCC Interrupt Status Register ISR (for detailed information see chapter ‘ISR - Interrupt Status Register’). TPCE863 User Manual Issue 1.0.1 Page 59 of 72... -
Page 60: Serial Communication Controller
The receiver will store the frame data (including CRC) plus a status byte. Data in Transmit FIFO data Transmitted / Received Flag data CRC-16 CRC-32 Flag Data Stream Data in Receive FIFO data CRC-16 CRC-32 RSTA Figure 7-1 : HDLC Address Mode 0 TPCE863 User Manual Issue 1.0.1 Page 60 of 72... -
Page 61: Extended Transparent Mode
- detection of the programmable Termination Character (bit ’TCDE’ and bit field ’TC’ in register TCR). Additionally, the time-out event interrupt as an optional status information indicates that a certain time has elapsed since the reception of the last character (refer to register CCR1). TPCE863 User Manual Issue 1.0.1 Page 61 of 72... -
Page 62: Data Transmission
4 more bytes storage available before an overflow may occur. This provides sufficient time for the far end transmitter to react to the change in the RTS signal and stop sending more data. TPCE863 User Manual Issue 1.0.1 Page 62 of 72... -
Page 63: Clock Sources
Clock Sources The TPCE863 supports several clock sources for the transmitter and receiver circuits, controlled by the ACR register. Clock source options are three on board oscillators (14.7456 MHz, 24 MHz and 10 MHz), the external RxCLK and TxCLK inputs or the internal clock recovery circuit (DPLL). TxCLK can be an input for the internal transmit clock or an output providing a transmit clock monitor signal (see following figure). -
Page 64: Data Encoding
NRZI: A logical ‘0’ is indicated by a transition and a logical ‘1’ by no transition at the beginning of the bit cell. Transmit / Receiver Clock NRZI Figure 7-3 : NRZ and NRZI Data Encoding TPCE863 User Manual Issue 1.0.1 Page 64 of 72... -
Page 65: Fm0 And Fm1 Encoding
In the first half of the bit cell, the physical signal level corresponds to the logical value of the data bit. At the center of the bit cell this level is inverted. The transmit clock precedes the receive clock by 90°. Transmit Clock Receiver Clock Manchester Figure 7-5 : Manchester Data Encoding TPCE863 User Manual Issue 1.0.1 Page 65 of 72... -
Page 66: Clock Recovery (Dpll)
16 (ACR.TCS = ‘100’) or to be the transmit clock generated by the DPLL circuit (ACR.TCS = ‘011’). The mechanism for the DPLL clock recovery depends on the selected data encoding (see chapter “Data Encoding”). TPCE863 User Manual Issue 1.0.1 Page 66 of 72... -
Page 67: Configuration Hints
AD[23..16] Byte 3 AD[31..24] The TPCE863 expects all accesses by the host/CPU and all data structures in the host/system RAM to be ‘Little Endian’. Transmit data in lower bytes is sent first. Receive data that was received earlier is stored at lower bytes. -
Page 68: Additional Termination Resistors
The control I/O lines (RTS, CTS, CD) are connected to LTC2844 transceivers without on-chip termination, as termination of these signals is not necessary in the normal case. If the application requires on board termination for these lines please contact TEWS TECHNOLOGIES. TPCE863 User Manual Issue 1.0.1... -
Page 69: Transmit & Receive Clock Polarity
Board Level Board Level RS422 Type Cable Interface TXCINV = 0 RXCINV = 0 RS422 Type Cable Interface TXCINV = 1 RXCINV = 1 Figure 8-1 : Transmit & Receive Clock Polarity TPCE863 User Manual Issue 1.0.1 Page 69 of 72... -
Page 70: Table 9-1 : On Board Leds
9 Module Management On Board LEDs For a quick visual inspection the TPCE863 provides on board LEDs at the component side. These indicate correct voltage supply and FPGA configuration state. Color Description DONE Green Shows whether the FPGA has configured or not Green PCIe Connector provided 3.3V voltage is valid... -
Page 71: Figure 10-1 : Front Panel I/O Connector Numbering
10 Pin Assignment – I/O Connector 10.1 Front Panel I/O Connector AMP 787082-7 or compatible Figure 10-1 : Front Panel I/O Connector Numbering TPCE863 User Manual Issue 1.0.1 Page 71 of 72... -
Page 72: Table 10-1 : Front I/O Pin Assignment
TXCA/- TXCA/- TXCB/+ TXCB/+ RXCA/- RXCA/- RXCB/+ RXCB/+ DSRB/+ DTRB/+ DSRA/- DTRA/- Table 10-1 : Front I/O Pin Assignment In V.28 (single-ended) mode, only the signals ending with “A” are used. TPCE863 User Manual Issue 1.0.1 Page 72 of 72...
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