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Summary of Contents for SiRF SiRFatlasV
- Page 1 Design Guide SiRFatlasV Power Supply January 2010 Document Number: CS-200241-DD Issue 3 NTRODUCTION This document describes the guidelines for designing the SiRFatlasV™ power supply system, including the schematics and PCB layout guide. SiRF Proprietary and Confidential...
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Page 2: Table Of Contents
Power Supply Design Guide Table of Contents Introduction ........................i SiRFatlasV Package Definition ..................1 SiRFatlasV Power Related Pins ................... 2 Power System........................ 5 SiRFatlasV Power Related Schematic ................. 6 Decoupling Capacitors For the Power Input Pad ............6 PCB Layout Examples ....................7 Top Layer Inductor, Capacitors Placement .................. - Page 3 Table 4: Switching DC/DC, LDOs, Comparator, and Reset Circuit Specification ........6 List of Figures Figure 1: SiRFatlasV Package Definition....................1 Figure 2: SiRFatlasV Based System PCB Layer Definition ............... 7 Figure 3: Top Layer Inductor, Capacitors Placement................8 Figure 4: Power Layer Partition........................ 9 Figure 5: VDD_CORE Plane on Layer 3 ....................
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Page 4: Sirfatlasv Package Definition
SiRFatlasV Power Supply Design Guide SiRFatlasV P ACKAGE EFINITION Figure 1: SiRFatlasV Package Definition January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 5: Sirfatlasv Power Related Pins
EN_DCDC1 Enable control of DCDC1, active high Switch pin for DCDC2, connect to inductor PGND2 GND for DCDC2 Input to adjust output voltage of DCDC2 through external resistor DEFDCDC2 divider January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 6: Table 1: Power Pin List
Voltage comparator input, connect to external resistor divider HYSTERESIS Input for hysteresis on threshold, connect to external resistor divider COMPO Voltage comparator output, open-drain output, active low Table 1: Power Pin List January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 7: Table 2: Ground Pin List
I/O ground for oscillator VSS_TSC Digital ground for internal touch screen controller. VSSA_TSC Analog ground for the Touch Screen Controller. VSSA_USB Analog ground for USB PHY VSSIO_DAC MoDAC ground Table 2: Ground Pin List January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 8: Power System
3.3V(1.62~3.63) Table 3: SiRFatlasV Electrical Characteristics In order to decrease system BOM and PCB size, SiRFatlasV integrates switching DC/DC and LDOs through SIP with a PMU die. The first generation PMU die integrates two switching DC/DC, four LDOs and one voltage comparator, and the second generation PMU die will add an additional LDO for RTC domain power and a reset circuit for the RTC domain logic’s reset. -
Page 9: Sirfatlasv Power Related Schematic
TSC/ADC periphera /MoDAC) Table 4: Switching DC/DC, LDOs, Comparator, and Reset Circuit Specification ATLAS OWER ELATED CHEMATIC Contact a SiRF FAE for the SiRFatlasV typical mini application system schematic. ECOUPLING APACITORS OR THE OWER NPUT Refer to the , the following decoupling capacitors are recommended for the design: mini application system ... -
Page 10: Pcb Layout Examples
PCB L AYOUT XAMPLES The SiRFatlasV package and ball-map definition is targeted for the 6-layer PCB layout, with a 16-bit DRAM interface and optimized high-speed signal integrity design. It has the following features: Removes serial resistors from the DRAM interface. -
Page 11: Top Layer Inductor, Capacitors Placement
By defining the switching DCDC and LDO’s output on the outer side of the BGA package, it is easy to put inductors and bypass capacitors close to these regulators’ output ball. January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 12: Power Layer Partition
VDD_MEM is on the right side of the SoC package. VDD_CORE is in the middle of the SoC package. It is easy to divide the power layer into three main power domains: VDDIO VDD_CORE VDD_MEM January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 13: Vdd_Core Plane On Layer 3
SiRFatlasV Power Supply Design Guide VDD_CORE Plane on Layer 3 Figure 5: VDD_CORE Plane on Layer 3 January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 14: Signal Fan Out Pattern And Bypass Capacitors For Cpu Power On Bottom Layer
As in this example, there is space to put 18 bypass capacitors close to the power balls, so the power noise can be controlled through the bypass capacitors. January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 15: Figure 7: Placement Of Decoupling Capacitors For Vdd_Core
Figure 7: Placement of Decoupling Capacitors for VDD_CORE The six pins highlighted by yellow circles in the following figure represent the placement of decoupling capacitors for VDDIO_MEM. Figure 8: Placement of Decoupling Capacitors for VDDIO_MEM January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 16: Figure 9: Placement Of Decoupling Capacitors For Vddio, Vddio_N, Vddio_L
Figure 9: Placement of Decoupling Capacitors for VDDIO, VDDIO_N, VDDIO_L The pin highlighted by a yellow circle in the following figure represents the placement of decoupling capacitors for VDDIO_DAC. Figure 10: Placement of Decoupling Capacitors for VDDIO_DAC January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 17: Figure 11: Increase Trace Width In Top Layer
Figure 12: Increase Trace Width in Bottom Layer Add more decoupling capacitors near the DDR2’s pin pad and increase the trace width. At the same time, route DDR2’s Vref trace in the same layer with the DDR2 chip. January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 18: Figure 13: Route Ddr2'S Vref Trace In The Same Layer With The Ddr2 Chip
SiRFatlasV Power Supply Design Guide Figure 13: Route DDR2’s Vref Trace in the Same Layer with the DDR2 Chip January, 2010 SiRF Design Guide – Proprietary and Confidential... - Page 19 SiRF Technology, Inc. reserves the right to make changes in its products, specifications and other information at any time without notice. SiRF assumes no liability or responsibility for any claims or damages arising out of the use of this document, or from the use of integrated circuits based on this document, including, but not limited to claims or damages based on infringement of patents, copyrights or other intellectual property rights.
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