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Design Guide
SiRFatlasV
Hardware Design Guide
January 2010
Document Number: CS-129512-UG
Issue 3
I
NTRODUCTION
This document serves as a hardware design guide for the SiRFatlasV™ SoC based Evaluation Board
(EVB) including boot configuration, power supply, and peripheral interfaces such as RAM, ROM, USB
and more. For details about the schematics, contact SiRF field application engineers (FAE).
SiRF Proprietary and Confidential
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Summary of Contents for SiRF SiRFatlasV
- Page 1 Issue 3 NTRODUCTION This document serves as a hardware design guide for the SiRFatlasV™ SoC based Evaluation Board (EVB) including boot configuration, power supply, and peripheral interfaces such as RAM, ROM, USB and more. For details about the schematics, contact SiRF field application engineers (FAE).
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Page 2: Table Of Contents
SD/MMC/MMC+ Controller ..................2 USB Connectivity ....................2 Packaging......................2 Temperature Range......................2 SiRFatlasV Syste m Block Diagram .................. 3 Boot Configuration ......................4 Power Supply ........................5 Power Pins ........................5 Decoupling CAP and Placement on the PCB Board ............... 6 Power Consumption ...................... - Page 3 SD/MMC ..........................10 PCB Layout ........................11 LCD…..........................11 PCB Layout ........................11 Crystal ..........................11 PCB Layout ........................12 GPIO............................ 12 Reset Button Connection ....................12 Avoid I/O Leakage During SoC Power-Off ..............14 SiRF Design Guide – Proprietary and Confidential January, 2010...
- Page 4 Table 4: Reset Behavior......................13 Table 5: Reset Behavior when Working as a Reset Button ..............14 List of Figures Figure 1: SiRFatlasV System Block Diagram .................. 3 Figure 2: USB DP/DN Route......................8 Figure 3: USB Layout Rule ......................9 Figure 4: ADC Power Supply and Reference Decoupling ..............10 Figure 5: SD0 Power Circuit .......................11...
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Page 5: Sirfatlasv Feature List
Two USP ports for PCM, DSP, I S, SPI, UART mode Two I C ports 12-bit ADC with 4-wire touch screen controller and 3 channel analog input, stream measurement mode for low cost audio input SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 6: Nand Flash Storage
Can be Host, Device or OTG Transfer up to 480Mbps Packaging 10mm x 13mm 285 ball TFBGA with 0.65mm pitch Temperature Range -20° C ~ +70° C extended commercial grade SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 7: Sirfatlasv System Block Diagram
SiRFatlasV Hardware Design Guide SiRFatlasV S YSTEM LOCK IAGRAM Figure 1: SiRFatlasV System Block Diagram SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 8: Boot Configuration
Hardware Design Guide ONFIGURATION SiRFatlasV supports many types of boot media including NAND Flash and SD cards. The boot mode can be set through the mode configuration pins according to the table below. NOTE – Set the pins with pull-up or pull-down resistors (10 kOhm to 100 kOhm), do not leave these pins set to float. -
Page 9: Power Supply
PLL GND VDDIO_OSC OSC Pad power VSSIO_OSC OSC PAD GND VDD_USB USB core digital power VDDA_USB USB analog power VSSA_USB USB GND VDD_TSC TSC core digital power VSS_TSC TSC core GND SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 10: Decoupling Cap And Placement On The Pcb Board
The on-chip power management unit (PMU) covers two DCDC converters (dcdc1, dcdc2), and four to five LDOs. NOTE – There are two versions of the PMU for SiRFatlasV: the first version has four LDOs (LDO1~4), and the second version has five LDOs. -
Page 11: Modac
ODAC Refer to CS-130255-UG SiRFatlasV Audio Hardware Design Guide for the Modac design. UART There are two UARTs on the SiRFatlasV chip, but only UART0 has the DMA function. Use UART0 to transmit large amounts of data at high speed. -
Page 12: Usp
NAND Add a pull-up resistor on the pin X_DF_WP_B since it is open drain. DRAM Refer to CS-129773-UG SiRFatlasV DDR2/mDDR Hardware Design Guide. Pay attention to the following when designing the USB module: Add ESD devices to the DP/DN and ID pins. -
Page 13: Tsc/Adc
Use as many vias as possible when changing between metal layers. Power supply decoupling should follow the figure below. The capacitors should be good quality ceramic and that they must be placed as close to the chip as possible. SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 14: Sd/Mmc
(see R307 to Q303 in Figure 5.) The reason for doing this is: The iNAND may not reboot normally if it did not discharge after power-off. SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 15: Pcb Layout
Add an EMI filter to all nets. PCB Layout All nets should be routed as equal length. RYSTAL The following figures are recommended circuits for the external crystal clock input. Figure 6: 24MHz Crystal Circuit SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 16: Pcb Layout
ESET UTTON ONNECTION SiRFatlasV has several reset function pins: X_RTC_RST_B This is a reset signal used to reset all RTC domain logic and power on/off control logic. After the VDDIO_RTC first powers on, X_RTC_RST_B should be active to guarantee that the RTC logic is reset and the power on/off control logic enters the RTC_COLDBOOT state. -
Page 17: Table 4: Reset Behavior
“low”; “Yes” means the SoC power is supplied, the logic module is reset. For details about the resets, refer to CS-130805-DS SiRFatlasV Datasheet. If the GPS device has a reset button, it is recommended to use warm-reset or X_REST_B to connect to this reset button. -
Page 18: Avoid I/O Leakage During Soc Power-Off
URING OWER The SiRFatlasV SoC has an ESD protection circuit between the I/O pad’s power and the I/O pad, when the I/O pad is not powered there is an external source to drive this pad “high” or “toggle”, therefore there may be leakage from the external source to the I/O power, and this may result in system instability. -
Page 19: Figure 9: Random Rtc Reset Or On Key 15S Issue
15s issue happens, x_system_en or x_dram_en goes to low to disable most of the SoC regulators. If, before the SoC I/O and core power are fully discharged, there is a way to pull X_RESET_B to low rapidly, SiRF Design Guide – Proprietary and Confidential January, 2010... -
Page 20: Figure 10: Workaround For Random Rtc Reset Or On Key 15S Issue
The hardware design should guarantee these control signals are set to “disable” at the default reset stage, check the SiRFatlasV Datasheet pin list to find every I/O pad’s reset status, then based on the peripheral’s enable/disable level, add external pull-up or pull-down resisters to make sure all these enable signals are in “disable”... - Page 21 Use the SoC’s I/O to control the switch or control the external module’s power supply to make sure that when system goes into deep-sleep or hibernation mode, the external module is powered off at same time SiRF Design Guide – Proprietary and Confidential January, 2010...
- Page 22 SiRF Technology, Inc. reserves the right to make changes in its products, specifications and other information at any time wi thout notice. SiRF assumes no liability or responsibility for any claims or damages arising out of the use of this document, or from the use of integrated circuits based on this document, including, but not limited to claims or damages based on infringement of paten ts, copyrights or other intellectual property rights.
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