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Summary of Contents for SiRF SiRFatlasV
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Page 1: Introduction
Design Guide SiRFatlasV Audio Hardware Design Guide January 2010 Document Number: CS-130255-UG Issue 2 NTRODUCTION This document serves as a hardware design guide for SiRFatlasV audio, including the input and output paths. SiRF Proprietary and Confidential... -
Page 2: Table Of Contents
Figure 5: Frequency Response of Headphone RC Filter ................7 Figure 6: Input Audio Chain ........................8 Figure 7: Pre-amplifier Circuit ........................9 Figure 8: A-weighted Filter Frequency Response ................... 11 January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 3: Audio Output Path
Audio Hardware Design Guide UDIO UTPUT The SiRFatlasV audio output path is built using pure digital IP DigDAC. DigDAC Overview DigDAC is a digital Virtual Component. The DigDAC architecture uses an entirely digital approach to convert digital source input to a PWM signal output. This virtual component features a flexible clock management system in order to eliminate external audio PLL requirements. -
Page 4: Application Information
DigDAC setting: Volume = 0dB (0x79h) When testing the SNR, set the input signal to 0 to get the noise floor of the headphone output. Sample rate: 48K/s Speaker Circuit Design Figure 2: Speaker Circuit January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 5: Figure 3: Frequency Response Of Rc Filter
The differential pair should be symmetrical, and it should be laid out and tightly surrounded by ground. For the audio amplifier, follow the design guide specifications. January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 6: Headphone
DigDAC setting: R/L channel volume = 0dB (0x79h) When testing the SNR, set the input signal to 0 to get the noise floor of the headphone output. Sample Rate: 48K/s Headphone Circuit Design Figure 4: Headphone Circuit January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 7: Figure 5: Frequency Response Of Headphone Rc Filter
All the audio traces (HEADPHONE_L, HEADPHONE_R, HPL, HPR, and so on) should be 10mil in width, and tightly surrounded by ground. The left channel and right channel should be separated by ground, but kept apart enough to avoid crosstalk. January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 8: Audio Input Path
UDIO NPUT By using an external pre-amplifier and an internal SAR ADC, the SiRFatlasV system forms an audio input path which interfaces with a single ended microphone. Figure 6 is the audio input path diagram. Figure 6: Input Audio Chain Pre-amplifier The input audio path uses the Maxim MAX9814 as a PGA. -
Page 9: Application Information
= 1/(2*Pi* Rin*Cin) -3dB The input impedance of MAX9814 is 100kOhm. Power Supply The MAX9814 and ADC should share the same (PMU_LDO1) power source. January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 10: Rc Buffer
Make X_AUX0 as short as possible. Put R8 and C5 close to SiRFatlasV. Put power decoupling capacitors (C1 and C2) as close as possible to the power pin. ... -
Page 11: Terminology
Figure 8: A-weighted Filter Frequency Response Jitter is the dynamic deviation of event instants in a stream or signal from their ideal positions in time, excluding modulation components below 10Hz. January, 2010 SiRF Design Guide – Proprietary and Confidential... -
Page 12: January, 2010 Sirf Design Guide – Proprietary And Confidential
SiRF Technology, Inc. reserves the right to make changes in its products, specifications and other information at any time without notice. SiRF assumes no liability or responsibility for any claims or damages arising out of the use of this document, or from the use of integrated circuits based on this document, including, but not limited to claims or damages based on infringement of patents, copyrights or other intellectual property rights.
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