SMSC LAN9311i Datasheet

Two port 10/100 managed ethernet switch with 16-bit non-pci cpu interface

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PRODUCT FEATURES

Highlights

High performance and full featured 2 port switch with

VLAN, QoS packet prioritization, Rate Limiting, IGMP

Snooping and management functions

Easily interfaces to most 16-bit embedded CPU's

Unique Virtual PHY feature simplifies software

development by mimicking the multiple switch ports

as a single port MAC/PHY

Integrated IEEE 1588 Hardware Time Stamp Unit

Target Applications

Cable, satellite, and IP set-top boxes

Digital televisions

Digital video recorders

VoIP/Video phone systems

Home gateways

Test/Measurement equipment

Industrial automation systems

Key Benefits

Ethernet Switch Fabric

— 32K buffer RAM

— 1K entry forwarding table

— Port based IEEE 802.1Q VLAN support (16 groups)

– Programmable IEEE 802.1Q tag insertion/removal

— IEEE 802.1d spanning tree protocol support

— QoS/CoS Packet prioritization

– 4 dynamic QoS queues per port

– Input priority determined by VLAN tag, DA lookup,

TOS, DIFFSERV or port default value

– Programmable class of service map based on input

priority

– Remapping of 802.1Q priority field on per port basis

– Programmable rate limiting at the ingress/egress

ports with random early discard, per port / priority

— IGMP v1/v2/v3 snooping for Multicast packet filtering

— IPV6 Multicast Listener Discovery snoop

— Programmable filter by MAC address

Switch Management

— Port mirroring/monitoring/sniffing: ingress and/or egress

traffic on any ports or port pairs

— Fully compliant statistics (MIB) gathering counters

— Control registers configurable on-the-fly

SMSC LAN9311/LAN9311i

LAN9311/LAN9311i

Two Port 10/100 Managed

Ethernet Switch with 16-Bit

Non-PCI CPU Interface

Ports

— 2 internal 10/100 PHYs with HP Auto-MDIX support

— Fully compliant with IEEE 802.3 standards

— 10BASE-T and 100BASE-TX support

— Full and half duplex support

— Full duplex flow control

— Backpressure (forced collision) half duplex flow control

— Automatic flow control based on programmable levels

— Automatic 32-bit CRC generation and checking

— Automatic payload padding

— 2K Jumbo packet support

— Programmable interframe gap, flow control pause value

— Full transmit/receive statistics

— Auto-negotiation

— Automatic MDI/MDI-X

— Loop-back mode

High-performance host bus interface

— Provides in-band network communication path

— Access to management registers

— Simple, SRAM-like interface

— 16-bit data bus

— Big, little, and mixed endian support

— Large TX and RX FIFO's for high latency applications

— Programmable water marks and threshold levels

— Host interrupt support

IEEE 1588 Hardware Time Stamp Unit

— Global 64-bit tunable clock

— Master or slave mode per port

— Time stamp on TX or RX of Sync and Delay_req

packets per port, Timestamp on GPIO

— 64-bit timer comparator event generation (GPIO or IRQ)

Comprehensive Power Management Features

— Wake on LAN

— Wake on link status change (energy detect)

— Magic packet wakeup

— Wakeup indicator event signal

Other Features

— General Purpose Timer

— Serial EEPROM interface (I

master) for non-managed configuration

— Programmable GPIOs/LEDs

Single 3.3V power supply

Available in Commercial & Industrial Temp. Ranges

DATASHEET

Datasheet

C master or Microwire

Revision 1.4 (08-19-08)

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Summary of Contents for SMSC LAN9311i

Page 1: Product Features
PRODUCT FEATURES Highlights High performance and full featured 2 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP Snooping and management functions Easily interfaces to most 16-bit embedded CPU’s Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports...
Page 2: Order Numbers
Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
Page 3: Table Of Contents
Switch Fabric Interrupts ........
Page 4 Chapter 6 Switch Fabric ........
Page 5 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.1.6 100M Phase Lock Loop (PLL) ... 86 7.2.2 100BASE-TX Receive ............87 7.2.2.1...
Page 6 10.2.3.3 ERAL (Erase All)... 147 10.2.3.4 EWDS (Erase/Write Disable) ... 147 10.2.3.5 EWEN (Erase/Write Enable)... 148 10.2.3.6 READ (Read Location) ... 148 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DATASHEET Datasheet SMSC LAN9311/LAN9311i...
Page 7 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3.7 WRITE (Write Location) ... 149 10.2.3.8 WRAL (Write All)... 149 10.2.4 EEPROM Loader ............150 10.2.4.1...
Page 8 14.2.6 Switch Fabric ........
Page 9 Switch Fabric Control and Status Registers ........
Page 10 14.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) ... 403 14.5.3.33 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII) ... 404 14.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) ... 405 14.5.3.35...
Page 11 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing ....... . . 451 15.5.8 PIO Write Cycle Timing .
Page 12 Figure 2.1 Internal LAN9311/LAN9311i Block Diagram ........
Page 13 Figure 14.1 LAN9311/LAN9311i Base Register Memory Map ....... . 167...
Page 14 Table 3.10 No-Connect Pins ............35 Table 4.1 Reset Sources and Affected LAN9311/LAN9311i Circuitry ......37 Table 4.2 Soft-Strap Configuration Strap Definitions.
Page 15 Table 16.2 LAN9311/LAN9311i 128-XVTQFP Dimensions........459...
Page 16: Chapter 1 Preface
First In First Out buffer Finite State Machine General Purpose I/O Host Bus Interface. The physical bus connecting the LAN9311/LAN9311i to the host. Also referred to as the Host Bus. Host Bus Interface Controller. The hardware module that interfaces theLAN9311/LAN9311i to the HBI.
Page 17 “1” and leaves the signal unchanged for a “0” Not Applicable No Connect Organizationally Unique Identifier Refers to data output from the LAN9311/LAN9311i to the host Program I/O cycle. An SRAM-like read or write cycle on the HBI. Parallel In Serial Out Phase Locked Loop Precision Time Protocol Refers to a reserved bit field or address.
Page 18: Buffer Types
Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the LAN9311/LAN9311i. When connected to a load that must be pulled low, an external resistor must be added. Analog input...
Page 19: Register Nomenclature
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Register Nomenclature Table 1.2 describes the register bit attribute notation used throughout this document. REGISTER BIT TYPE NOTATION Read: A register or bit with this attribute can be read.
Page 20: Chapter 2 Introduction
The LAN9311/LAN9311i provides 2 on-chip PHYs, 1 Virtual PHY and 3 MACs. The Virtual PHY and the Host MAC are used to connect the LAN9311/LAN9311i switch fabric to the host bus interface. All ports support automatic or manual full duplex flow control or half duplex backpressure (forced collision) flow control.
Page 21: Block Diagram
IEEE 1588 System Clocks/ Time Stamp Interrupt Reset/PME Free-Run Clock/Events Controller Controller External 25MHz Crystal Figure 2.1 Internal LAN9311/LAN9311i Block Diagram Virtual PHY Registers Host MAC MDIO TX/RX FIFOs Host Bus Interface Register To 16-bit Access Host Bus EEPROM Loader...
Page 22: System Clocks/Reset/Pme Controller
A multi-module reset is initiated by assertion of the following: Digital Reset - DIGITAL_RST (bit 0) in the - Resets all LAN9311/LAN9311i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY) Soft Reset - SRST (bit 0) in the...
Page 23: Switch Fabric
2.2.4 Ethernet PHYs The LAN9311/LAN9311i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface.
Page 24: Host Mac
1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9311/LAN9311i as a whole may function as a boundary clock.
Page 25: Gpio/Led Controller
LAN9311/LAN9311i system configuration and status registers. The LAN9311/LAN9311i utilizes the internal Host MAC to provide a network path for the host CPU. The LAN9311/LAN9311i may share the host bus with additional system memory and/or peripherals. For more information on the HBI, refer to Chapter 8, "Host Bus Interface (HBI),"...
Page 26: Chapter 3 Pin Description And Configuration
VDD33BIAS VDD18TX2 VDD33A2 RXP2 RXN2 VDD33A2 TXP2 TXN2 Figure 3.1 LAN9311 128-VTQFP Pin Assignments (TOP VIEW) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface SMSC LAN9311 128-VTQFP TOP VIEW DATASHEET Datasheet VDD33IO END_SEL FIFO_SEL...
Page 27: 128-Xvtqfp Pin Diagram
VDD18TX1 EXRES VDD33BIAS VDD18TX2 VDD33A2 RXP2 RXN2 VDD33A2 TXP2 TXN2 Figure 3.2 LAN9311/LAN9311i 128-XVTQFP Pin Assignments (TOP VIEW) SMSC LAN9311/LAN9311i SMSC LAN9311/LAN9311i 128-XVTQFP TOP VIEW NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND DATASHEET VDD33IO END_SEL...
Page 28: Pin Descriptions
Pin Descriptions This section contains the descriptions of the LAN9311/LAN9311i pins. The pin descriptions have been broken into functional groups as follows: LAN Port 1 Pins LAN Port 2 Pins LAN Port 1 & 2 Power and Common Pins Host Bus Interface Pins...
Page 29: Table 3.2 Lan Port 2 Pins
EXRES Bias Reference: Used for internal bias circuits. Connect to an external 12.4K ohm, 1% resistor to ground. +3.3V Port 1 Analog Power Supply Refer to the LAN9311/LAN9311i application note for additional connection information. DATASHEET DESCRIPTION (LED_CFG), LED Configuration Register...
Page 30: Table 3.4 Host Bus Interface Pins
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface BUFFER TYPE +3.3V Port 2 Analog Power Supply Refer to the LAN9311/LAN9311i application note for additional connection information. +3.3V Master Bias Power Supply Refer to the LAN9311/LAN9311i application note for additional connection information.
Page 31: Table 3.5 Eeprom Pins
BUFFER TYPE Data FIFO Direct Access Select: When driven high, all accesses to the LAN9311/LAN9311i are directed to the RX and TX Data FIFO’s. All reads are from the RX Data FIFO, and all writes are to the TX Data FIFO. In this mode, the address input is ignored.
Page 32: Table 3.6 Dedicated Configuration Strap Pins
LED_EN Strap PHY Address PHY_ADDR_SEL Strap Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 3.5 EEPROM Pins (continued) BUFFER TYPE EECS EEPROM Microwire Chip Select: In Microwire EEPROM mode (EEPROM_TYPE = 0), this pin is the Microwire EEPROM chip select output.
Page 33: Table 3.7 Miscellaneous Pins
(IRQ_CFG). For more information, refer to Chapter 5, "System Interrupts," on page nRST System Reset Input: This active low signal allows external hardware to reset the LAN9311/LAN9311i. (PU) The LAN9311/LAN9311i also contains an internal power-on reset circuit. Thus, this signal may be left unconnected if an external hardware reset is not needed.
Page 34: Table 3.8 Pll Pins
BUFFER TYPE PLL +1.8V Power Supply: This pin must be connected to VDD18CORE for proper operation. Refer to the LAN9311/LAN9311i application note for additional connection information. ICLK Crystal Input: External 25MHz crystal input. This signal can also be driven by a single-ended clock oscillator.
Page 35: Table 3.10 No-Connect Pins
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 3.9 Core and I/O Power and Ground Pins (continued) NAME SYMBOL 18,48,80, Common 97,112,113, Ground Note 3.8 Note 3.8 Plus external pad for 128-XVTQFP package only NAME...
Page 36: Chapter 4 Clocking, Resets, And Power Management
455. Resets The LAN9311/LAN9311i provides multiple hardware and software reset sources, which allow varying levels of the LAN9311/LAN9311i to be reset. All resets can be categorized into three reset types as described in the following sections: Chip-Level Resets —Power-On Reset (POR) —nRST Pin Reset...
Page 37: Chip-Level Resets
(RESET_CTL), read access to any internal resources is forbidden while the READY bit is cleared. Writes to any address are invalid until the READY bit is set. Note: The LAN9311/LAN9311i must be read at least once after any chip-level reset to ensure that write operations function properly.
Page 38: Nrst Pin Reset
Writes to any address are invalid until the READY bit is set. Note: The digital reset and soft reset do not reset register bits designated as NASR. Note: The LAN9311/LAN9311i must be read at least once after a multi-module reset to ensure that write operations function properly.
Page 39: Soft Reset (Srst)
Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared. No other modules of the LAN9311/LAN9311i are affected by this reset. In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY power-down mode.
Page 40: Virtual Phy Reset
4.2.4 Configuration Straps Configuration straps allow various features of the LAN9311/LAN9311i to be automatically configured to user defined values. Configuration straps can be organized into two main categories: hard-straps and soft-straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST).
Page 41: Table 4.2 Soft-Strap Configuration Strap Definitions
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions STRAP NAME DESCRIPTION LED_en_strap[7:0] LED Enable Straps: Configures the default value for the LED_EN bits in the (LED_CFG). A high value configures the associated LED/GPIO pin as a LED.
Page 42 When configured low, full-duplex Pause packet detection and generation are disabled. When configured high, full- duplex Pause packet detection and generation are enabled. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Speed Select LSB (PHY_SPEED_SEL_LSB) Section Port x PHY Basic...
Page 43 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) STRAP NAME DESCRIPTION manual_FC_strap_1 Port 1 Manual Flow Control Enable Strap: Configures the default value of the Select (MANUAL_FC_1) Control Register...
Page 44 When configured low, full-duplex Pause packet detection and generation are disabled. When configured high, full- duplex Pause packet detection and generation are enabled. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Speed Select LSB (PHY_SPEED_SEL_LSB) Section Port x PHY Basic...
Page 45: Hard-Straps
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) STRAP NAME DESCRIPTION manual_FC_strap_2 Port 2 Manual Flow Control Enable Strap: Configures the default value of the Select (MANUAL_FC_2) Control Register...
Page 46: Power Management
PHYs and Virtual PHY as detailed in Power Management The LAN9311/LAN9311i Port 1 and Port 2 PHYs and the Host MAC support several power management and wakeup features. The LAN9311/LAN9311i can be programmed to issue an external wake signal (PME) via several methods, including wake on LAN, wake on link status change (energy detect), and magic packet wakeup.
Page 47: Port 1 & 2 Phy Power Management
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet WUFR (bit 6) of HMAC_WUCSR register WUEN (bit 2) of HMAC_WUCSR register MPR (bit 5) of HMAC_WUCSR register MPEN (bit 1) of HMAC_WUCSR register INT7 (bit 7) of...
Page 48: Host Mac Power Management
Refer to Section 9.5, "Wake-up Frame Detection," on page 117 Detection," on page 119 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface (PMT_CTRL). Power Management Control Register (PMT_CTRL) (PMT_CTRL). for additional details on these features.
Page 49: Chapter 5 System Interrupts
System Interrupt Controller. The programmable system interrupts are generated internally by the various LAN9311/LAN9311i sub-modules and can be configured to generate a single external host interrupt via the IRQ interrupt output pin. The programmable nature of the host interrupt provides the user with the ability to optimize performance dependent upon the application requirements.
Page 50: Figure 5.1 Functional Interrupt Register Hierarchy
INT_STS register Bit 12 (GPIO) of INT_STS register Figure 5.1 Functional Interrupt Register Hierarchy Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1588 Time Stamp Interrupt Register 1588_INT_STS_EN Switch Fabric Interrupt Registers SW_IMR...
Page 51: 1588 Time Stamp Interrupts
Chapter 14, "Register Descriptions," on page 167 5.2.1 1588 Time Stamp Interrupts Multiple 1588 Time Stamp interrupt sources are provided by the LAN9311/LAN9311i. The top-level 1588_EVNT (bit 29) of the event occurred in the 1588 Interrupt Status and Enable Register 1588 Interrupt Status and Enable Register (1588_INT_STS_EN) status of all 1588 interrupt conditions.
Page 52: Ethernet Phy Interrupts
For additional details on the Ethernet PHY interrupts, refer to page 5.2.4 GPIO Interrupts Each GPIO[11:0] of the LAN9311/LAN9311i is provided with its own interrupt. The top-level GPIO (bit 12) of the Interrupt Status Register (INT_STS) in the General Purpose I/O Interrupt Status and Enable Register Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and status of each GPIO[11:0] interrupt.
Page 53: Power Management Interrupts
Host MAC operation. 5.2.6 Power Management Interrupts Multiple Power Management Event interrupt sources are provided by the LAN9311/LAN9311i. The top- level PME_INT (bit 17) of the Management interrupt event occurred in the Power Management Control Register (PMT_CTRL) Power Management conditions.
Page 54: Software Interrupt
Enable Register (INT_EN). The READY interrupt (bit 30) of the indicates that the LAN9311/LAN9311i is ready to be accessed after a power-up or reset condition. Writing a 1 to this bit in the In order for a device ready interrupt event to trigger the external IRQ interrupt pin, bit 30 of the...
Page 55: Chapter 6 Switch Fabric
Chapter 6 Switch Fabric Functional Overview At the core of the LAN9311/LAN9311i is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames. The switch fabric provides an extensive feature set which includes...
Page 56: Switch Fabric Csr Writes
Datasheet 6.2.1 Switch Fabric CSR Writes To perform a write to an individual switch fabric register, the desired data must first be written into the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA). The write cycle is initiated by p e r f o r m i n g a s i n g l e w r i t e t o t h e...
Page 57: Switch Fabric Csr Reads
Figure 6.1 Switch Fabric CSR Write Access Flow Diagram 6.2.2 Switch Fabric CSR Reads To perform a read of an individual switch fabric register, the read cycle must be initiated by performing a single write to the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the desired register address, the R_nW (bit 30) set, and the AUTO_INC and AUTO_DEC fields cleared.
Page 58: Flow Control Enable Logic
6.2.3 Flow Control Enable Logic Each switch fabric port (0,1,2) is provided with two flow control enable inputs per port, one for transmission and one for reception. Flow control on transmission allows the transmitter to generate back pressure in half-duplex mode, and pause packets in full-duplex. Flow control in reception enables the reception of pause packets to pause transmissions.
Page 59: Table 6.1 Switch Fabric Flow Control Enable Logic
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet register. When Auto-negotiation is enabled and the MANUAL_FC_x bit is cleared, the switch port flow control enables during full-duplex are determined by Auto-negotiation. Note: The flow control values in the...
Page 60: 10/100 Ethernet Macs
Case 11 - Asymmetric pause from partner (towards switch port) 10/100 Ethernet MACs The switch fabric contains three 10/100 MAC blocks, one for each switch port (0,1,2). The 10/100 MAC provides the basic 10/100 Ethernet functionality, including transmission deferral and collision back- off/retry, receive/transmit FCS checking and generation, receive/transmit pause flow control, and transmit back pressure.
Page 61: Receive Counters
The size of the RX FIFO is 256 bytes. If a bad packet with less than 64 bytes is received, it will be flushed from the FIFO automatically and the FIFO space recovered. Packets equal to or larger than 64 bytes with an error will be marked and reported to the switch engine. The switch engine will subsequently drop the packet.
Page 62: Transmit Mac
The auto-padding and FCS generation is controlled via the TX Pad Enable bit of the Transmit Configuration Register The transmit FIFO acts as a temporary buffer between the transmit MAC and the switch engine. The FIFO logic manages the re-transmission for normal collision conditions or discards the frames for late or excessive collisions.
Page 63: Switch Engine (Swe)
Total collision count Switch Engine (SWE) The switch engine (SWE) is a VLAN layer 2 (link layer) switching engine supporting 3 ports. The SWE supports the following types of frame formats: untagged frames, VLAN tagged frames, and priority tagged frames. The SWE supports both the 802.3 and Ethernet II frame formats.
Page 64: Learning/Aging/Migration
Switch Engine ALR Command Status Register Engine ALR Write Data 0 Register Register (SWE_ALR_WR_DAT_1). Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface (SWE_PORT_INGRSS_CFG). for additional details. S w i t c h E n g i n e...
Page 65 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The following procedure should be followed in order to add, delete, and modify the ALR entries: 1. Write the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) bits.
Page 66: Forwarding Rules
If there is insufficient buffer space, the packet is discarded. When the switch is enabled for VLAN support, these following rules also apply: If the packet is untagged or priority tagged and the Admit Only VLAN bit for the ingress port is set, the packet is filtered.
Page 67: Transmit Priority Queue Selection
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.3 Transmit Priority Queue Selection The transmit priority queue may be selected from five options. As shown in be based on: the static value for the destination address in the ALR table...
Page 68: Figure 6.5 Switch Engine Transmit Queue Calculation
IP Precedence Queue = ALR Priority Figure 6.5 Switch Engine Transmit Queue Calculation Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface for definitions of the configuration bits. Get Queue Packet from Host DA Highest...
Page 69: Port Default Priority
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.4.3.1 Port Default Priority As detailed in Figure 6.5, the default priority is based on the ingress ports priority bits in its port VID value. The PVID table is read and written by using the...
Page 70: Vlan Support
6.4.4 VLAN Support The switch engine supports 16 active VLANs out of a possible 4096. The VLAN table contains the 16 active VLAN entries, each consisting of the VID, the port membership, and un-tagging instructions. Member Un-tag Member Port 2...
Page 71: Ingress Flow Metering And Coloring
6.4.6 Ingress Flow Metering and Coloring The LAN9311/LAN9311i supports hardware ingress rate limiting by metering packet streams and marking packets as either Green, Yellow, or Red according to three traffic parameters: Committed Information Rate (CIR), Committed Burst Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does not exceed the CBS, Yellow if it exceeds to CBS but not the EBS, or Red otherwise.
Page 72: Ingress Flow Calculation
The VLAN tag priority field (but not through the per port Priority Regeneration table) The port default Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 6.3 Typical Ingress Rate Settings 80 nS 100 nS...
Page 73: Figure 6.7 Switch Engine Ingress Flow Priority Selection
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Packet is from Host Packet is Tagged VL Higher Priority Use Precedence IPv4(TOS) IPv6(TC) IPv4 Precedence Source Port VLAN Priority Figure 6.7 Switch Engine Ingress Flow Priority Selection...
Page 74: Broadcast Storm Control
6.4.7 Broadcast Storm Control In addition to ingress rate limiting, the LAN9311/LAN9311i supports hardware broadcast storm control on a per port basis. This feature is enabled via the (SWE_BCST_THROT). The allowed rate per port is specified as the number of bytes multiplied by 64 allowed to be received every 1.72 mS interval.
Page 75: Port Mirroring
VLAN. 6.4.9 Port Mirroring The LAN9311/LAN9311i supports port mirroring where packets received or transmitted on a port or ports can also be copied onto another “sniffer” port. Port mirroring is configured using the Multiple mirrored ports can be defined, but only one sniffer port can be defined.
Page 76: Packets To The Host Cpu
VID field. Note: The maximum size tagged packet that can normally be sent into a switch port (from the Host MAC) is 1522 bytes. Since the special tag consumes four bytes of the packet length, the outgoing packet is limited to 1518 bytes, even if it contains a regular VLAN tag as part of the packet data.
Page 77: Buffer Manager (Bm)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Buffer Manager (BM) The buffer manager (BM) provides control of the free buffer space, the multiple priority transmit queues, transmission scheduling, and packet dropping. VLAN tag insertion and removal is also performed by the buffer manager.
Page 78: Transmit Priority Queue Servicing
The egress limiting is enabled per priority queue. After a packet is selected to be sent, its length is recorded. The switch then waits a programmable amount of time, scaled by the packet length, before servicing that queue once again. The amount of time per byte is programmed into the Buffer Manager Egress Rate registers (refer to definitions).
Page 79: Adding, Removing, And Changing Vlan Tags
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 6.5.6 Adding, Removing, and Changing VLAN Tags Based on the port configuration and the received packet formation, a VLAN tag can be added to, removed from, or modified in a packet. There are four received packet type cases: non-tagged, priority- tagged, normal-tagged, and CPU special-tagged.
Page 80: Figure 6.9 Hybrid Port Tagging And Un-Tagging
Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Figure 6.9. Receive Tag...
Page 81: Counters
Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) Switch Fabric Interrupts The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch engine, and MACs. These interrupts are detailed in page SMSC LAN9311/LAN9311i Section 5.2.2, "Switch Fabric Interrupts,"...
Page 82: Chapter 7 Ethernet Phys
Chapter 7 Ethernet PHYs Functional Overview The LAN9311/LAN9311i contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port.
Page 83: Port 1 & 2 Phys
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Port 1 & 2 PHYs Functionally, each PHY can be divided into the following sections: 100BASE-TX Transmit 10BASE-T Transmit PHY Auto-negotiation HP Auto-MDIX MII MAC Interface PHY Management Control Note 7.1...
Page 84: 100Base-Tx Transmit
For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface. The MII MAC Interface is described in detail in Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
Page 85: Table 7.2 4B/5B Code Table
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet CODE GROUP 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 IDLE 11000 First nibble of SSD, translated to “0101”...
Page 86: Scrambler And Piso
The 100M PLL locks onto the reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE-TX Transmitter. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 7.2 4B/5B Code Table (continued) RECEIVER...
Page 87: 100Base-Tx Receive
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 7.2.2 100BASE-TX Receive The 100BASE-TX receive data path is shown in to the PHY. Each major block is explained in the following sections. Internal MII Receive Clock Port x...
Page 88: Nrzi And Mlt-3 Decoding
(bad SSD error), RXER is asserted and the value 1110b is driven onto the internal receive data bus (RXD) to the switch fabric MAC. Note that the internal MII’s data valid signal (RXDV) is not yet asserted when the bad SSD occurs.
Page 89: 10Base-T Transmit
For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface. The MII MAC Interface is described in detail in Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
Page 90: Mii Mac Interface
IEEE 802.3 specification. The LAN9311/LAN9311i does not support “Next Page” capability. Many of the default advertised capabilities of the PHY are determined via configuration straps as shown in PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x),"...
Page 91 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10M PLL (analog) 10M TX Driver (analog) Auto-negotiation is started by the occurrence of any of the following events: Power-On Reset (POR) Hardware reset (nRST) PHY Software reset (via...
Page 92: Phy Pause Flow Control
7.2.5.2 Parallel Detection If the LAN9311/LAN9311i is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard.
Page 93: Half Vs. Full-Duplex
MII MAC Interface The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and from the switch fabric MAC. The PHY is connected internally to the switch fabric MAC via standard MII signals per IEEE 802.3.
Page 94: Phy Management Control
PHY Power-Down Modes There are two power-down modes for the PHY: PHY General Power-Down PHY Energy Detect Power-Down Note: For more information on the various power management features of the LAN9311/LAN9311i, refer to Section 4.3, "Power Management," on page Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Section 14.4.2, "Port 1 &...
Page 95: Phy General Power-Down
The energy detect power down feature is part of the broader power management features of the LAN9311/LAN9311i and can be used to trigger the power management event output pin (PME). This is accomplished by enabling the energy detect power-down feature of the PHY as described above,...
Page 96: Phy Software Reset Via Phy_Basic_Ctrl_X
Power-Down Modes," on page 94 7.2.11 LEDs Each PHY provides LED indication signals to the GPIO/LED block of the LAN9311/LAN9311i. This allows external LEDs to be used to indicate various PHY related functions such as TX/RX activity, speed, duplex, or link status. Refer to information on the configuration of these signals.
Page 97: Parallel Detection
Note: For the Virtual PHY, the auto-negotiation register bits (and management of such) are used by the Host MAC. So the perception of local and link partner is reversed. The local device is the Host MAC, while the link partner is the switch fabric. This is consistent with the intention of the Virtual PHY.
Page 98: Virtual Phy Pause Flow Control
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY supports three block specific resets. These are is discussed in the following sections. For detailed information on all LAN9311/LAN9311i resets, refer to 7.3.2.1 Virtual PHY Software Reset via RESET_CTL The Virtual PHY can be reset via the (VPHY_RST).
Page 99: Chapter 8 Host Bus Interface (Hbi)
System Control and Status Registers (CSRs). These registers are accessible to the host via the Host Bus Interface and allow direct (and indirect) access to all the LAN9311/LAN9311i functions. For a full list of all System CSR’s and their descriptions, refer to Control and Status Registers".
Page 100: 16-Bit Bus Writes
However, this is not a fatal error. The LAN9311/LAN9311i will reset its read counters and restart a new cycle on the next read. Note: Some registers are readable as 16-bit registers. In this case, if desired, only one 16-bit read may be performed without the need to read the other word.
Page 101: Figure 8.1 Little Endian Byte Ordering
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet SMSC LAN9311/LAN9311i 16-BIT LITTLE ENDIAN (END_SEL = 0) INTERNAL ORDER A[1] = 1 A[1] = 0 HOST DATA BUS Figure 8.1 Little Endian Byte Ordering 16-BIT BIG ENDIAN...
Page 102: Host Interface Timing
Some registers are readable during reset. The reset condition may terminate between halves of a 16- bit read pair. In this case, the LAN9311/LAN9311i does not require 16-bit read to complete the DWORD cycle. Reads to other registers during reset are not supported, and may lead to unintended behavior.
Page 103: Table 8.1 Read After Write Timing Rules
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet REGISTER NAME RX Data FIFO RX Status FIFO RX Status FIFO PEEK TX Status FIFO TX Status FIFO PEEK ID_REV IRQ_CFG INT_STS INT_EN BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG...
Page 104 1588_CLOCK_ADDEND 1588_CLOCK_TARGET_HI 1588_CLOCK_TARGET_LO 1588_CLOCK_TARGET_RELOAD_HI 1588_CLOCK_TARGET_RELOAD_LO 1588_AUX_MAC_HI 1588_AUX_MAC_LO Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) (ASSUMING T DATASHEET Datasheet NUMBER OF BYTE_TEST READS...
Page 105 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 8.1 Read After Write Timing Rules (continued) REGISTER NAME 1588_CONFIG 1588_INT_STS_EN MANUAL_FC_1 MANUAL_FC_2 MANUAL_FC_MII SWITCH_CSR_DATA SWITCH_CSR_CMD E2P_CMD E2P_DATA LED_CFG VPHY_BASIC_CTRL VPHY_BASIC_STATUS VPHY_ID_MSB VPHY_ID_LSB VPHY_AN_ADV VPHY_AN_LP_BASE_ABILITY VPHY_AN_EXP VPHY_SPECIAL_CONTROL_STATUS...
Page 106: Special Restrictions On Back-To-Back Read Cycles
There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific registers after reading a resource that has side effects. In many cases there is a delay between reading the LAN9311/LAN9311i, and the subsequent indication of the expected change in the control and status register values.
Page 107: Pio Reads
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 8.5.4 PIO Reads PIO reads can be used to access System CSR’s or RX Data and RX/TX Status FIFOs. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Read cycle begins when both nCS and nRD are asserted.
Page 108: Pio Burst Reads
A[4:1] nCS, nRD D[15:0] (OUTPUT) Figure 8.4 Functional Timing for PIO Burst Read Operation Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 15.9, “PIO Burst Read Cycle Timing Values,” on VALID VALID VALID...
Page 109: Rx Data Fifo Direct Pio Reads
RX Data FIFO Direct PIO Reads In this mode only A[2:1] are decoded, and any read of the LAN9311/LAN9311i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
Page 110: Rx Data Fifo Direct Pio Burst Reads
RX Data FIFO Direct PIO Burst Reads In this mode only A[2:1] are decoded, and any burst read of the LAN9311/LAN9311i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
Page 111: Pio Writes
8.5.8 PIO Writes PIO writes are used for all LAN9311/LAN9311i write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must de-assert between cycles for the period specified in Values,”...
Page 112: Tx Data Fifo Direct Pio Writes
TX Data FIFO Direct PIO Writes In this mode only A[2:1] are decoded, and any write to the LAN9311/LAN9311i will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
Page 113: Chapter 9 Host Mac
Host Bus Interface (HBI) and the Ethernet PHYs and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO). An additional bus is used to access the Host MAC CSR’s via the...
Page 114: Flow Control
System CSR space and the Host MAC CSR space. Note: The Host MAC controls the flow between the switch fabric and the Host MAC, not the network flow control. The switch fabric handles the network flow control independently.
Page 115: Address Filtering
Note: This filtering function is performed after any switch fabric filtering functions. The user must ensure the switch filtering is setup properly to allow packets to be passed to the Host MAC for further filtering.
Page 116: Perfect Filtering
9.4.2 Hash Only Filtering This type of filtering checks for incoming receive packets (from switch Port 0) with either multicast or physical destination addresses, and executes an imperfect address filtering against the hash table. The hash table is formed by merging the values in the...
Page 117: Inverse Filtering
Note: The switch fabric must be configured to pass wake-up packets to the Host MAC for this function to operate properly. Note: When wake-up frame detection is enabled via the WUEN bit of the...
Page 118: Table 9.2 Wake-Up Frame Filter Register Structure
RESERVED Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask...
Page 119: Magic Packet Detection
Host MAC examines received data for a Magic Packet. The LAN9311/LAN9311i can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the HMAC_WUCSR register is set.
Page 120: Host Mac Address
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC Note: The switch fabric must be configured to pass magic packets to the Host MAC for this function to operate properly.
Page 121: Fifos
For more information on the EEPROM and EEPROM Loader, refer to Master EEPROM Controller," on page FIFOs The LAN9311/LAN9311i contains four host-accessible FIFOs (TX Status, RX Status, TX Data, and RX Data) and two internal inaccessible Host MAC TX/RX MIL FIFO’s (TX MIL FIFO, RX MIL FIFO). 9.7.1...
Page 122: Fifo Memory Allocation Configuration
RX Status TX Data RX Data Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Host MAC RX Dropped Frames Counter Hardware Configuration Register TX FIFO Size (TX_FIF_SZ) (HW_CFG). The TX_FIF_SZ field selects the total allocation for the TX data...
Page 123: Tx Data Path Operation
Transmitter Error (TXE) flag is asserted. The LAN9311/LAN9311i can be programmed to start payload transmission of a buffer on a byte boundary by setting the “Data Start Offset” field in the TX command. The “Data Start Offset” field points to the actual start of the payload data within the first 8 DWORDs of the buffer.
Page 124: Figure 9.3 Simplified Host Tx Flow Diagram
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet The LAN9311/LAN9311i can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9311/LAN9311i is operating in a system that always performs multi-word bursts.
Page 125: Tx Buffer Format
Figure 9.4 shows the TX Buffer as it is written into the LAN9311/LAN9311i. It should be noted that not all of the data shown in this diagram is actually stored in the TX Data FIFO. This must be taken into account when calculating the actual TX Data FIFO usage.
Page 126: Tx Command 'A
This value, along with the Buffer End Alignment field, is read and checked by the LAN9311/LAN9311i and used to determine how many extra DWORDs were added to the end of the Buffer. A running count is also maintained in the LAN9311/LAN9311i of the cumulative buffer sizes for a given packet.
Page 127: Tx Command 'B
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.8.2.2 TX Command ‘B’ BITS 31:16 Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status word and can be used by the host to correlate TX status words with their corresponding packets.
Page 128: Calculating Worst-Case Tx Mil Fifo Usage
TX Status FIFO overruns. In this mode the host is responsible for re-synchronizing TX status in the case of an overrun. Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events described in the TX Status word may still occur.
Page 129: Calculating Actual Tx Data Fifo Usage
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16 collisions while attempting to transmit the current packet. Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.
Page 130: Figure 9.5 Tx Example 1
Last Segment = 1 Buffer Size = 17 TX Command 'B' Packet Length = 111 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Memory Mapped TX Data FIFO Port TX Command 'A' Data Passed to the...
Page 131: Tx Example 2
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.8.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet is in a single buffer as follows: 2-Byte “Data Start Offset”...
Page 132: Transmitter Errors
TX_ON bit. If the there are frames pending in the TX Data FIFO (i.e., TX Data FIFO was not purged), the transmission will resume with this data. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Transmit Configuration Register Interrupt Status Register...
Page 133: Rx Data Path Operation
RX packets, but it must not be changed during an RX packet read. The LAN9311/LAN9311i can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9311/LAN9311i is operating in a system that always performs multi-DWORD bursts.
Page 134: Figure 9.7 Host Receive Routine Using Interrupts
Last Packet Figure 9.7 Host Receive Routine Using Interrupts Last Packet Figure 9.8 Host Receive Routine Using Polling Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface init Idle RX Interrupt Read RX Status DWORD...
Page 135: Receive Data Fifo Fast Forward
The RX data path implements an automatic data discard function. Using the RX Data FIFO Fast Forward bit (RX_FFWD) in the instruct the LAN9311/LAN9311i to skip the packet at the head of the RX Data FIFO. The RX Data FIFO pointers are automatically incremented to the beginning of the next RX packet.
Page 136: Rx Status Format
9.9.3 RX Status Format Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events described in the RX Status word may still occur. BITS Reserved. This bit is reserved. Reads 0. Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing filtering.
Page 137: Stopping And Starting The Receiver
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 9.9.4 Stopping and Starting the Receiver To stop the receiver, the host must clear the RXEN bit in the When the receiver is halted, the RXSTOP_INT will be pulsed and reflected in the Register (INT_STS).
Page 138: Chapter 10 Serial Management
The I The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the LAN9311/LAN9311i at reset. The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs, and the system CSRs. 10.2...
Page 139: Eeprom Controller Operation
Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the EWEN command must first be issued. If an operation is attempted and the EEPROM device does not respond within 30mS, the LAN9311/LAN9311i will time-out, and the EPC_TIMEOUT bit of the (E2P_CMD) will be set.
Page 140: I2C Eeprom
(EPC_ADDRESS) of the EEPROM Command Register address bits, while the smaller EEPROMs treat the upper address bits as don’t cares. The EEPROM Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Idle Write Write...
Page 141: I2C Protocol Overview
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet controller drives all the address bits as requested regardless of the actual size of the EEPROM. The supported size ranges for I eeprom_size_strap[0] # OF ADDRESS BYTES Note 10.1 Bits in the control byte are used as the upper address bits.
Page 142: I2C Eeprom Device Addressing
Control Byte Address Byte S 1 0 1 0 Chip / Block R/~W Select Bits Single Byte Addressing Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface C cycle. data data data stable change change...
Page 143: I2C Eeprom Byte Read
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.2.3 C EEPROM Byte Read Following the device addressing, a data byte may be read from the EEPROM by outputting a start condition and control byte with a control code of 1010b, chip/block select bits as described in Section 10.2.2.2, and the R/~W bit high.
Page 144: I2C Eeprom Byte Writes
For a register level description of a write operation, refer to Operation," on page 139. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface is set. C master will poll the EEPROM to determine when the byte C EEPROM byte write.
Page 145: Microwire Eeprom
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3 Microwire EEPROM Based on the configuration strap eeprom_type_strap, various sized Microwire EEPROMs are supported. The varying size ranges are supported by additional bits in the address field...
Page 146: Erase (Erase Location)
EECLK EEDO EEDI Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface ADDRESS 0 0 X X X X X X X 1 1 X X X X X X X A8 A7 A6 A5 A4 A3 A2 A1 A0...
Page 147: Eral (Erase All)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3.3 ERAL (Erase All) If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM. The EPC_TIMEOUT bit of the EEPROM does not respond within 30mS.
Page 148: Ewen (Erase/Write Enable)
EECS EECLK EEDO EEDI Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Figure 10.10 EEPROM EWEN Cycle (E2P_CMD). The result of the read is available in the Figure 10.11 EEPROM READ Cycle DATASHEET Datasheet...
Page 149: Datasheet
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 10.2.3.7 WRITE (Write Location) If erase/write operations are enabled in the EEPROM, this command will cause the contents of the EEPROM Data Register (E2P_DATA) EPC_ADDRESS field of the...
Page 150: Eeprom Loader
(E2P_CMD), the EPC_BUSY bit in the While the EEPROM Loader is active, the READY bit of the (HW_CFG) Power Management Control Register (PMT_CTRL) LAN9311/LAN9311i should be attempted. The operational flow of the EEPROM Loader can be seen Figure 10.14. Revision 1.4 (08-19-08)
Page 151: Figure 10.14Eeprom Loader Flow Diagram
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet DIGITAL_RST, nRST, POR, RELOAD EPC_BUSY = 1 Read Byte 0 Byte 0 = A5h Read Bytes 1-6 Write Bytes 1-6 into Host MAC and switch MAC Address Registers...
Page 152: Eeprom Valid Flag
Host MAC Address High Register (HMAC_ADDRH) (HMAC_ADDRL). During this time, the EPC_BUSY bit in the (E2P_CMD) is set. Note: The switch MAC address registers are not reloaded due to this condition. 10.2.4.4 Soft-Straps The 7 byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this...
Page 153: 4.2Virtual Phy Registers Synchronization
Optionally following the configuration strap values, the EEPROM data may be formatted to allow access to the LAN9311/LAN9311i parallel, directly writable registers. Access to indirectly accessible registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of EEPROM space).
Page 154: Eeprom Loader Finished Wait-State
31h, 32h, 33h, 34h, 35h, 36h, 37h, 38h, 39h, 3Ah, 3Bh, 3Ch (4 x count3 of data) In order to avoid overwriting the Switch CSR register interface or the PHY Management Interface (PMI), the EEPROM Loader waits until the CSR Busy bit of the...
Page 155: Chapter 11 Ieee 1588 Hardware Time Stamp Unit
Time stamping is supported on all ports, with an individual IEEE 1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9311/LAN9311i as a whole may function as a boundary clock.
Page 156: Block Diagram
11.1.2 Block Diagram The LAN9311/LAN9311i IEEE 1588 implementation is illustrated in following major function blocks: IEEE 1588 Time Stamp These three identical blocks provide time stamping functions on all switch fabric ports. IEEE 1588 Clock This block provides a 64-bit tunable clock that is used as the time source for all IEEE 1588 time stamp related functions.
Page 157: Ieee 1588 Time Stamp
PHY. This is consistent with the point-of-view of where the partner clock resides (LAN9311/LAN9311i receives packets from the partner via the PHY, etc.). For the time stamp module connected to the Host MAC (Port 0), the definition of transmit and receive is reversed. Receive is defined as data from the switch fabric, while transmit is defined as data to the switch fabric.
Page 158: Capture Locking
14.2.5.22, "1588 Configuration Register (1588_CONFIG)," on page 223 the capture locking related bits. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 11.2 details the time stamp capture delay as a function of the Chapter 7, "Ethernet PHYs,"...
Page 159: Ptp Message Detection
11.2.2 PTP Message Detection In order to provide the most flexibility, loose packet type matching is used by the LAN9311/LAN9311i. This assumes that for all packets received with a valid FCS, only the MAC destination address is required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in the PTP protocol: 224.0.1.129 through 224.0.1.132.
Page 160: Ieee 1588 Clock
IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9311/LAN9311i. It is readable and writable by the host via the (1588_CLOCK_HI) In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads are required to fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a wrong intermediate value could be read.
Page 161: Ieee 1588 Clock/Events
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 11.4 IEEE 1588 Clock/Events The IEEE 1588 Clock/Events block is responsible for generating and controlling all IEEE 1588 clock related events. A 64-bit comparator is included in this block which compares the 64-bit IEEE 1588 clock...
Page 162: Chapter 12 General Purpose Timer & Free-Running Clock
Clock. 12.1 General Purpose Timer The LAN9311/LAN9311i provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system interrupts. The resolution of this timer is 100uS. The GPT loads the General Purpose Timer Count Register (GPT_CNT)
Page 163: Chapter 13 Gpio/Led Controller
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Chapter 13 GPIO/LED Controller 13.1 Functional Overview The GPIO/LED Controller provides 12 configurable general purpose input/output pins, GPIO[11:0]. These pins can be individually configured to function as inputs, push-pull outputs, or open drain outputs and each is capable of interrupt generation with configurable polarity.
Page 164: Gpio Ieee 1588 Timestamping
13.2.2 GPIO Interrupts Each GPIO of the LAN9311/LAN9311i provides the ability to trigger a unique GPIO interrupt in the General Purpose I/O Interrupt Status and Enable Register GPIO_INT[11:0] bits of this register provides the current status of the corresponding interrupt, and each interrupt is enabled by setting the corresponding GPIO_INT_EN[11:0] bit.
Page 165: Ieee 1588 Gpio Interrupts
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet GPIO_INT_POL[9:8] bits also determine the polarity of the clock events as described in Section 13.2.1.2. 13.2.2.2 IEEE 1588 GPIO Interrupts In addition to the standard GPIO interrupts in the...
Page 166 The various LED indication functions shown in TX Port 0 - The signal is pulsed low for 80mS to indicate activity from the switch fabric to the Host MAC. This signal is then driven high for a minimum of 80mS, after which the process will repeat if TX activity is again detected.
Page 167: Chapter 14 Register Descriptions
Note: Register bit type definitions are provided in Note: Not all LAN9311/LAN9311i registers are memory mapped or directly addressable. For details on the accessibility of the various LAN9311/LAN9311i registers, refer the register sub-sections listed above.
Page 168: Tx/Rx Fifo Ports
14.1.3 Direct FIFO Access Mode When the FIFO_SEL pin is driven high, the LAN9311/LAN9311i enters the direct FIFO access mode. In this mode, all host write operations are to the TX Data FIFO and all host read operations are from the RX Data FIFO.
Page 169: System Control And Status Registers
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2 System Control and Status Registers The System CSR’s are directly addressable memory mapped registers with a base address offset range of 050h to 2DCh. These registers are addressable by the Host via the Host Bus Interface (HBI).
Page 170 1588_CLOCK_HI_TX_CAPTURE_2 134h 1588_CLOCK_LO_TX_CAPTURE_2 138h 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Free Running Counter Register, Host MAC RX Dropped Frames Counter Register, Section 14.2.2.6 Host MAC CSR Interface Command Register, Section 14.2.2.7...
Page 171 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.1 System Control and Status Registers (continued) ADDRESS OFFSET SYMBOL 13Ch 1588_SRC_UUID_LO_TX_CAPTURE_2 140h 1588_CLOCK_HI_RX_CAPTURE_MII 144h 1588_CLOCK_LO_RX_CAPTURE_MII 148h 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII 14Ch 1588_SRC_UUID_LO_RX_CAPTURE_MII 150h 1588_CLOCK_HI_TX_CAPTURE_MII 154h 1588_CLOCK_LO_TX_CAPTURE_MII 158h 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_MII 15Ch...
Page 172 200h-2DCh SWITCH_CSR_DIRECT_DATA 2E0h-3FFh RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Port 1 Manual Flow Control Register, Port 2 Manual Flow Control Register, Port 0 Flow Control Register, Switch Fabric CSR Interface Data Register, Section 14.2.6.4...
Page 173: Interrupts
14.2.1 Interrupts This section details the interrupt related System CSR’s. These registers control, configure, and monitor the IRQ interrupt output pin and the various LAN9311/LAN9311i interrupt sources. For more information on the LAN9311/LAN9311i interrupts, refer to 14.2.1.1 Interrupt Configuration Register (IRQ_CFG) Offset: This read/write register configures and indicates the state of the IRQ signal.
Page 174 Note 14.1 Register bits designated as NASR are not reset when either the SRST bit in the Configuration Register (HW_CFG) Register (RESET_CTL) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION register or the DIGITAL_RST bit in the is set.
Page 175: Interrupt Status Register (Int_Sts)
Register (INT_EN) is set high. Writing a one clears this interrupt. Device Ready (READY) This interrupt indicates that the LAN9311/LAN9311i is ready to be accessed after a power-up or reset condition. 1588 Interrupt Event (1588_EVNT) This bit indicates an interrupt event from the IEEE 1588 module. This bit...
Page 176 This interrupt is generated when a packet larger than 2048 bytes has been received by the Host MAC. Note: This can occur when the switch engine adds a tag to a non-tagged jumbo packet that is originally larger than 2044 bytes. Receiver Error (RXE) Indicates that the Host MAC receiver has encountered an error.
Page 177 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS RX Status FIFO Full Interrupt (RSFF) This interrupt is generated when the RX Status FIFO is full. RX Status FIFO Level Interrupt (RSFL) This interrupt is generated when the RX Status FIFO reaches the...
Page 178: Interrupt Enable Register (Int_En)
TX Status FIFO Full Interrupt Enable (TSFF_EN) TX Status FIFO Level Interrupt Enable (TSFL_EN) RX Dropped Frame Interrupt Enable (RXDF_INT_EN) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 05Ch Size: 32 bits Interrupt Status Register (INT_STS) bits, which mimic the layout of this register.
Page 179 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS RESERVED - This bit must be written with 0b for proper operation. RX Status FIFO Full Interrupt Enable (RSFF_EN) RX Status FIFO Level Interrupt Enable (RSFL_EN) RESERVED...
Page 180: Fifo Level Interrupt Register (Fifo_Int)
Status FIFO used space is greater than this value, a Interrupt (RSFL) will be generated in the (INT_STS). Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 068h Size: DESCRIPTION will be generated. When the...
Page 181: Host Mac & Fifo's
RX End Alignment (RX_EA) This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9311/LAN9311i will add extra DWORD’s of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORD’s.
Page 182 (DWORD offset) may be modified while the receiver is running. Modifications to the upper bits will take affect on the next DWORD read. RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet TYPE...
Page 183: Transmit Configuration Register (Tx_Cfg)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.2 Transmit Configuration Register (TX_CFG) Offset: This register controls the Host MAC transmit functions. BITS 31:16 RESERVED Force TX Status Discard (TXS_DUMP) When a 1 is written to this bit, the TX Status FIFO is cleared of all pending status DWORD’s and the TX status pointers are cleared to zero.
Page 184: Receive Datapath Control Register (Rx_Dp_Ctrl)
Please refer to section Forward," on page 135 of RX_FFWD. 30:0 RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 078h Size: 32 bits DESCRIPTION Section 9.9.1.1, "Receive Data FIFO Fast for detailed information regarding the use...
Page 185: Rx Fifo Information Register (Rx_Fifo_Inf)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.4 RX FIFO Information Register (RX_FIFO_INF) Offset: This register contains the indication of used space in the RX FIFO’s. BITS 31:24 RESERVED 23:16 RX Status FIFO Used Space (RXSUSED) This field indicates the amount of space, in DWORD’s, currently used in the...
Page 186: Tx Fifo Information Register (Tx_Fifo_Inf)
This field indicates the amount of space, in bytes, available in the TX Data FIFO. The application should never write more than is available, as indicated by this value. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 080h Size: 32 bits...
Page 187: Host Mac Rx Dropped Frames Counter Register (Rx_Drop)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.6 Host MAC RX Dropped Frames Counter Register (RX_DROP) Offset: This register indicates the number of receive frames that have been dropped by the Host MAC. BITS 31:0...
Page 188: Host Mac Csr Interface Command Register (Mac_Csr_Cmd)
The index of each Host MAC CSR is defined Section 14.3, "Host MAC Control and Status Registers," on page Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 0A4h Size: Host MAC CSR Interface Data Register (MAC_CSR_DATA) Section 14.3, "Host MAC Control and Status...
Page 189: Host Mac Csr Interface Data Register (Mac_Csr_Data)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.2.8 Host MAC CSR Interface Data Register (MAC_CSR_DATA) Offset: This read-write register is used in conjunction with the (MAC_CSR_CMD) to indirectly access the Host MAC CSR’s. Note: The full list of Host MAC CSR’s are described in Registers,"...
Page 190: Host Mac Automatic Flow Control Configuration Register (Afc_Cfg)
Pause frames and backpressure are sent to the switch fabric to stop it from sending packets to the Host MAC. Network data into the switch fabric is affected only if the switch fabric buffering fills. Note: The Host MAC will not transmit pause frames or assert back pressure if the transmitter is disabled.
Page 191: Table 14.2 Backpressure Duration Bit Mapping
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS Flow Control on Multicast Frame (FCMULT) When this bit is set, the Host MAC will assert back pressure when the AFC level is reached and a multicast frame is received. This field has no function in full-duplex mode.
Page 192 Table 14.2 Backpressure Duration Bit Mapping (continued) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface BACKPRESSURE DURATION 300uS 350uS 400uS 450uS 500uS 550uS 600uS DATASHEET Datasheet 302.2uS 352.2uS 402.2uS 452.2uS 502.2uS 552.2uS 602.2uS SMSC LAN9311/LAN9311i...
Page 193: Gpio/Led
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3 GPIO/LED This section details the General Purpose I/O (GPIO) and LED related System CSR’s. 14.2.3.1 General Purpose I/O Configuration Register (GPIO_CFG) Offset: This read/write register configures the GPIO input and output pins. The polarity of the 12 GPIO pins is configured here as well as the IEEE 1588 timestamping and clock compare event output properties of the GPIO[9:8] pins.
Page 194 GPIO_EVENT_POL_8 and GPIO_EVENT_POL_9 bits determine when the corresponding pin is driven per the following table: GPIOx Clock Event Polarity Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 1588 Clock Event Pin State not driven...
Page 195: General Purpose I/O Data & Direction Register (Gpio_Data_Dir)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3.2 General Purpose I/O Data & Direction Register (GPIO_DATA_DIR) Offset: This read/write register configures the direction of the 12 GPIO pins and contains the GPIO input and output data bits.
Page 196: General Purpose I/O Interrupt Status And Enable Register (Gpio_Int_Sts_En)
As GPIO interrupts, GPIO inputs are level sensitive and must be active greater than 40 nS to be recognized as interrupt inputs. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1E8h Size: 32 bits...
Page 197: Led Configuration Register (Led_Cfg)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.3.4 LED Configuration Register (LED_CFG) Offset: This read/write register configures the GPIO[7:0] pins as LED[7:0] pins and sets their functionality. BITS 31:10 RESERVED LED Function 1-0 (LED_FUN[1:0]) These bits control the function associated with each LED pin as shown in Table 13.1...
Page 198: Eeprom
14.2.4 EEPROM This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been connected to the LAN9311/LAN9311i. Refer to chapter "I2C/Microwire Master EEPROM Controller," on page 138 modes (I C and Microwire) of the EEPROM Controller (EPC).
Page 199 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 30:28 EEPROM Controller Command (EPC_COMMAND) This field is used to issue commands to the EEPROM controller. The EEPROM controller will execute a command when the EPC_BUSY bit is set.
Page 200 This field is used by the EEPROM Controller to address a specific memory location in the serial EEPROM. This address must be byte aligned. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET...
Page 201: Eeprom Data Register (E2P_Data)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.4.2 EEPROM Data Register (E2P_DATA) Offset: This read/write register is used in conjunction with the perform read and write operations with the serial EEPROM. BITS 31:8 RESERVED EEPROM Data (EEPROM_DATA) This field contains the data read from or written to the EEPROM.
Page 202: Ieee 1588
1588 Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 203: Port X 1588 Clock Low-Dword Receive Capture Register (1588_Clock_Lo_Rx_Capture_X)
1588 Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 204: Port X 1588 Sequence Id, Source Uuid High-Word Receive Capture Register (1588_Seq_Id_Src_Uuid_Hi_Rx_Capture_X)
Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 205: Port X 1588 Source Uuid Low-Dword Receive Capture Register (1588_Src_Uuid_Lo_Rx_Capture_X)
Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 206: Port X 1588 Clock High-Dword Transmit Capture Register (1588_Clock_Hi_Tx_Capture_X)
1588 Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 207: Port X 1588 Clock Low-Dword Transmit Capture Register (1588_Clock_Lo_Tx_Capture_X)
1588 Sync or Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 208: Port X 1588 Sequence Id, Source Uuid High-Word Transmit Capture Register (1588_Seq_Id_Src_Uuid_Hi_Tx_Capture_X)
Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 209: Port X 1588 Source Uuid Low-Dword Transmit Capture Register (1588_Src_Uuid_Lo_Tx_Capture_X)
Delay_Req packet. Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9311/LAN9311i. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 210: Gpio 8 1588 Clock High-Dword Capture Register (1588_Clock_Hi_Capture_Gpio_8)
31:0 Timestamp High (TS_HI) This field contains the high 32-bits of the timestamp upon activation of GPIO Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 160h Size: 32 bits GPIO 8 1588 Clock Low-DWORD Capture Register form the 64-bit GPIO 8 timestamp capture.
Page 211: Gpio 8 1588 Clock Low-Dword Capture Register (1588_Clock_Lo_Capture_Gpio_8)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.10 GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) Offset: This read only register combined with the (1588_CLOCK_HI_CAPTURE_GPIO_8) BITS 31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO...
Page 212: Gpio 9 1588 Clock High-Dword Capture Register (1588_Clock_Hi_Capture_Gpio_9)
31:0 Timestamp High (TS_HI) This field contains the high 32-bits of the timestamp upon activation of GPIO Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 168h Size: 32 bits GPIO 9 1588 Clock Low-DWORD Capture Register form the 64-bit GPIO 9 timestamp capture.
Page 213: Gpio 9 1588 Clock Low-Dword Capture Register (1588_Clock_Lo_Capture_Gpio_9)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.12 GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) Offset: This read only register combined with the (1588_CLOCK_HI_CAPTURE_GPIO_9) BITS 31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO...
Page 214: 1588 Clock High-Dword Register (1588_Clock_Hi)
Note: The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHOT bit in the 1588 Command Register (1588_CMD) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 170h Size: 32 bits 1588 Clock Low-DWORD Register (1588_CLOCK_LO) accordingly.
Page 215: 1588 Clock Low-Dword Register (1588_Clock_Lo)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.14 1588 Clock Low-DWORD Register (1588_CLOCK_LO) Offset: This read/write register combined with 64-bit 1588 Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has...
Page 216: 1588 Clock Addend Register (1588_Clock_Addend)
This 32-bit value is added to the 1588 frequency divisor accumulator every cycle. This allows the base 100MHz frequency of the 64-bit 1588 Clock to be adjusted accordingly. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 178h Size: 32 bits...
Page 217: 1588 Clock Target High-Dword Register (1588_Clock_Target_Hi)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI) Offset: T h i s r e a d / w r i t e r e g i s t e r c o m b i n e d w i t h (1588_CLOCK_TARGET_LO) is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match.
Page 218: 1588 Clock Target Low-Dword Register (1588_Clock_Target_Lo)
(1588_CLOCK_TARGET_HI) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 180h Size: 1 5 8 8 C l o c k Ta r g e t H i g h - D W O R D R e g i s t e r form the 64-bit 1588 Clock Target value.
Page 219: 1588 Clock Target Reload High-Dword Register (1588_Clock_Target_Reload_Hi)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.18 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) Offset: This read/write register combined with (1588_CLOCK_TARGET_RELOAD_LO) Clock Target Reload is the value that is reloaded to the 1588 Clock Compare value when a clock...
Page 220: 1588 Clock Target Reload/Add Low-Dword Register (1588_Clock_Target_Reload_Lo)
Note: Both this register (1588_CLOCK_TARGET_RELOAD_HI) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 188h Size: 32 bits 1588 Clock Target Reload High-DWORD Register form the 64-bit 1588 Clock Target Reload value. The 1588 1588 Configuration Register (1588_CONFIG).
Page 221: 1588 Auxiliary Mac Address High-Word Register (1588_Aux_Mac_Hi)
1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) Offset: This read/write register combined with the (1588_AUX_MAC_LO) address can be enabled for each port of the LAN9311/LAN9311i via their respective User Defined MAC Address Enable bit in the 1588 Hardware Time Stamp Unit," on page 155 BITS...
Page 222: 1588 Auxiliary Mac Address Low-Dword Register (1588_Aux_Mac_Lo)
1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) Offset: This read/write register combined with the (1588_AUX_MAC_HI) address can be enabled for each port of the LAN9311/LAN9311i via their respective User Defined MAC Address Enable bit in the 1588 Hardware Time Stamp Unit," on page 155 BITS...
Page 223: 1588 Configuration Register (1588_Config)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.22 1588 Configuration Register (1588_CONFIG) Offset: This read/write register is responsible for the configuration of the 1588 timestamps for all ports. BITS Master/Slave Port 2 (M_nS_2) When set, Port 2 is a time clock master and captures timestamps when a Sync packet is transmitted and when a Delay_Req is received.
Page 224 Delay_Req packet is transmitted and when a Sync packet is received. Note: For Port 0, receive is defined as data from the switch fabric, while transmit is defined as data to the switch fabric. Primary MAC Address Enable Port 0(Host MAC) (MAC_PRI_EN_MII) This bit enables/disables the primary MAC address on Port 0.
Page 225 0: Disables RX Port 0 Lock 1: Enables RX Port 0 Lock Note: For Port 0, receive is defined as data from the switch fabric, while transmit is to the switch fabric. Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII) This bit enables/disables the TX lock. This lock prevents a 1588 capture from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX interrupt for Port 0 is ready set due to a previous capture.
Page 226 0: Reload upon a clock target compare event 1: Increment upon a clock target compare event Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION is already set General Purpose I/O...
Page 227: 1588 Interrupt Status And Enable Register (1588_Int_Sts_En)
PTP packet and the 1588 clock was captured. 1588 Port 0(Host MAC) RX Interrupt (1588_MII_RX_INT) This interrupt indicates that a packet from the switch fabric to the Host MAC the matches the configured PTP packet and the 1588 clock was captured.
Page 228 BITS 1588 Port 0(Host MAC) TX Interrupt (1588_MII_TX_INT) This interrupt indicates that a packet from the Host MAC to the switch fabric matches the configured PTP packet and the 1588 clock was captured. Note: For Port 0, receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 229: 1588 Command Register (1588_Cmd)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.5.24 1588 Command Register (1588_CMD) Offset: This register is used to issue 1588 commands. Using the clock snapshot bit allows the host to properly read the current IEEE 1588 clock values from the (1588_CLOCK_HI) Section 11.3, "IEEE 1588 Clock,"...
Page 230: Switch Fabric
This section details the memory mapped System CSR’s which are related to the Switch Fabric. The flow control of all three ports of the switch fabric can be configured via the memory mapped System CSR’s MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_MII. The MAC address used by the switch for Pause frames is configured via the SWITCH_MAC_ADDRH and SWITCH_MAC_ADDRL registers.
Page 231 If auto-negotiation is disabled, the RX_FC_1 and TX_FC_1 values are used. 1: TX_FC_1 and RX_FC_1 bits determine the flow control of switch Port 1 when in full-duplex mode Note 14.4 The default value of this field is determined by the BP_EN_strap_1 configuration strap. The strap values are loaded during reset and can be re-written by the EEPROM Loader.
Page 232: Port 2 Manual Flow Control Register (Manual_Fc_2)
Port 2 Manual Flow Control Register (MANUAL_FC_2) Offset: This read/write register allows for the manual configuration of the switch Port 2 flow control. This register also provides read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated. Refer to information.
Page 233 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note 14.8 The default value of this field is determined by the BP_EN_strap_2 configuration strap. The strap values are loaded during reset and can be re-written by the EEPROM Loader. Once the EEPROM Loader re-writes the values, this register is updated with the new values.
Page 234: Port 0(Host Mac) Manual Flow Control Register (Manual_Fc_Mii)
Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) Offset: This read/write register allows for the manual configuration of the switch Port 0(Host MAC) flow control. This register also provides read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated.
Page 235 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS Port 0 Transmit Flow Control Enable (TX_FC_MII) When the MANUAL_FC_MII bit is set, or Virtual Auto-Negotiation is disabled, this bit enables/disables full-duplex Pause packets to be generated on switch Port 0.
Page 236: Switch Fabric Csr Interface Data Register (Switch_Csr_Data)
Upon a read, the value returned depends on the R/nW bit in the Fabric CSR Interface Command Register set, the data is from the switch fabric. If R/nW is cleared, the data is the value that was last written into this register.
Page 237: Switch Fabric Csr Interface Command Register (Switch_Csr_Cmd)
27:20 RESERVED SMSC LAN9311/LAN9311i 1B0h Size: Switch Fabric CSR Interface Data Register to control the read and write operations to the various Switch Fabric CSR’s. DESCRIPTION (SWITCH_CSR_DATA). The Switch Fabric CSR Interface Data Register CSR Busy CSR Address Switch Fabric CSR Interface Data...
Page 238 15:0 CSR Address (CSR_ADDR[15:0]) This field selects the 16-bit address of the Switch Fabric CSR that will be accessed with a read or write operation. Refer to Accessible Switch Control and Status Registers,” on page 309 Switch Fabric CSR addresses.
Page 239: Switch Fabric Mac Address High Register (Switch_Mac_Addrh)
Offset: This register contains the upper 16-bits of the MAC address used by the switch for Pause frames. This r e g i s t e r i s u s e d i n c o n j u n c t i o n w i t h (SWITCH_MAC_ADDRL).
Page 240: Switch Fabric Mac Address Low Register (Switch_Mac_Addrl)
Offset: This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This r e g i s t e r i s u s e d i n c o n j u n c t i o n w i t h (SWITCH_MAC_ADDRH).
Page 241: Switch Fabric Csr Interface Direct Data Register (Switch_Csr_Direct_Data)
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) Offset: This write-only register set is used to perform directly addressed write operations to the Switch Fabric CSR’s. Using this set of registers, writes can be directly addressed to select Switch Fabric registers,...
Page 242 Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map (continued) REGISTER NAME MAC_TX_CFG_2 MAC_TX_FC_SETTINGS_2 MAC_IMR_2 SWE_ALR_CMD SWE_ALR_WR_DAT_0 SWE_ALR_WR_DAT_1 SWE_ALR_CFG SWE_VLAN_CMD SWE_VLAN_WR_DATA SWE_DIFFSERV_TBL_CMD SWE_DIFFSERV_TBL_WR_DATA SWE_GLB_INGRESS_CFG SWE_PORT_INGRESS_CFG SWE_ADMT_ONLY_VLAN SWE_PORT_STATE SWE_PRI_TO_QUE SWE_PORT_MIRROR SWE_INGRESS_PORT_TYP SWE_BCST_THROT SWE_ADMT_N_MEMBER SWE_INGRESS_RATE_CFG SWE_INGRESS_RATE_CMD SWE_INGRESS_RATE_WR_DATA SWE_INGRESS_REGEN_TBL_MII SWE_INGRESS_REGEN_TBL_1 SWE_INGRESS_REGEN_TBL_2 SWE_IMR...
Page 243 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map (continued) REGISTER NAME BM_FC_RESUME_LVL BM_BCST_LVL BM_RNDM_DSCRD_TBL_CMD BM_RNDM_DSCRD_TBL_WDATA BM_EGRSS_PORT_TYPE BM_EGRSS_RATE_00_01 BM_EGRSS_RATE_02_03 BM_EGRSS_RATE_10_11 BM_EGRSS_RATE_12_13 BM_EGRSS_RATE_20_21 BM_EGRSS_RATE_22_23 BM_VLAN_MII BM_VLAN_1 BM_VLAN_2 BM_IMR...
Page 244: Phy Management Interface (Pmi)
This field contains the value written to the PHYs. For a write operation, this register should be first written with the desired data. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface for additional information. 0A4h...
Page 245: Phy Management Interface Access Register (Pmi_Access)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.7.2 PHY Management Interface Access Register (PMI_ACCESS) Offset: This register is used to control the management cycles to the PHYs. A PHY access is initiated when this register is written. This register is used in conjunction with the Register (PMI_DATA) to perform write operations to the PHYs.
Page 246: Virtual Phy
All functionality and bit definitions comply with these standards. The IEEE 802.3 specified register index (in decimal) is included under the LAN9311/LAN9311i memory mapped offset of each Virtual PHY register as a reference. For additional information, refer to the IEEE 802.3 Specification.
Page 247: Virtual Phy Basic Control Register (Vphy_Basic_Ctrl)
1: Reset Loopback (VPHY_LOOPBACK) This bit enables/disables the loopback mode. When enabled, transmissions from the Host MAC are not sent to the switch fabric. Instead, they are looped back onto the receive path. 0: Loopback mode disabled (normal operation) 1: Loopback mode enabled...
Page 248 Note 14.16 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet...
Page 249: Virtual Phy Basic Status Register (Vphy_Basic_Status)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.2 Virtual PHY Basic Status Register (VPHY_BASIC_STATUS) Offset: Index (decimal): This register is used to monitor the status of the Virtual PHY. BITS 31:16 RESERVED (See Note 14.17) 100BASE-T4 This bit displays the status of 100BASE-T4 compatibility.
Page 250 Note 14.22 The VIrtual PHY supports basic and some extended register capability. The Virtual PHY supports Registers 0-6 (per the IEEE 802.3 specification). Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION for additional details.
Page 251: Virtual Phy Identification Msb Register (Vphy_Id_Msb)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.3 Virtual PHY Identification MSB Register (VPHY_ID_MSB) Offset: Index (decimal): This read/write register contains the MSB of the Virtual PHY Organizationally Unique Identifier (OUI). The LSB of the Virtual PHY OUI is contained in the (VPHY_ID_LSB).
Page 252: Virtual Phy Identification Lsb Register (Vphy_Id_Lsb)
DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide. Note 14.26 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1CCh Size: 32 bits...
Page 253: Virtual Phy Auto-Negotiation Advertisement Register (Vphy_An_Adv)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.5 Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV) Offset: Index (decimal): This read/write register contains the advertised ability of the Virtual PHY and is used in the Auto- Negotiation process with the link partner.
Page 254 Note 14.32 The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this field. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION Section 4.2.4, "Configuration Straps," on...
Page 255: Virtual Phy Auto-Negotiation Link Partner Base Page Ability Register (Vphy_An_Lp_Base_Ability)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.6 Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) Offset: Index (decimal): This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto- Negotiation process with the Virtual PHY.
Page 256: Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values
100BASE-X half duplex, 10BASE-T full duplex, and 10BASE-T half duplex. For more information on the Virtual PHY auto-negotiation, see Negotiation," on page Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION Pause bits of the (VPHY_AN_ADV).
Page 257: Virtual Phy Auto-Negotiation Expansion Register (Vphy_An_Exp)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.8.7 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) Offset: Index (decimal): This register is used in the Auto-Negotiation process. BITS 31:16 RESERVED (See Note 14.37) 15:5 RESERVED Parallel Detection Fault This bit indicates whether a Parallel Detection Fault has been detected.
Page 258: Virtual Phy Special Control/Status Register (Vphy_Special_Control_Status)
Switch Looopback MII When set, transmissions from the switch fabric Port 0(Host MAC) are not sent to the Host MAC. Instead, they are looped back into the switch engine. From the MAC viewpoint, this is effectively a FAR LOOPBACK. If loopback is enabled during half-duplex operation, then the Enable Receive...
Page 259 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Note 14.42 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide.
Page 260: Miscellaneous
Miscellaneous This section details the remainder of the System CSR’s. These registers allow for monitoring and configuration of various LAN9311/LAN9311i functions such as the Chip ID/revision, byte order testing, power management, hardware configuration, general purpose timer, and free running counter.
Page 261: Byte Order Test Register (Byte_Test)
Section 8.4, "Host Endianess," on page 100 Note: This register can be read while the LAN9311/LAN9311i is in the reset or not ready states. Note: Either half of this register can be read without the need to read the other half.
Page 262: Hardware Configuration Register (Hw_Cfg)
122. Note: This register can be polled while the LAN9311/LAN9311i is in the reset or not ready state (READY bit is cleared). Note: Either half of this register can be read without the need to read the other half.
Page 263 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 19:16 TX FIFO Size (TX_FIF_SZ) This field sets the size of the TX FIFOs in 1KB values to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the space allocated by TX_FIF_SIZ, and the TX Data FIFO consumes the remaining space specified by TX_FIF_SZ.
Page 264: Power Management Control Register (Pmt_Ctrl)
Note: This register is one of only four registers (the others are HW_CFG, BYTE_TEST, and RESET_CTL) which can be polled while the LAN9311/LAN9311i is in the reset or not ready state (READY bit is cleared). Note: Either half of this register can be read without the need to read the other half.
Page 265 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS Wake-On-LAN Enable (WOL_EN) When set, the PME signal (if enabled via the PME_EN bit) will be asserted in accordance with the PME_IND bit upon a WOL event. When set, the...
Page 266 BITS Device Ready (READY) When set, this bit indicates that the LAN9311/LAN9311i is ready to be accessed. Upon power-up, nRST reset, soft reset, or digital reset, the host processor may interrogate this field as an indication that the LAN9311/LAN9311i has stabilized and is fully active.
Page 267: General Purpose Timer Configuration Register (Gpt_Cfg)
General Purpose Timer Configuration Register (GPT_CFG) Offset: This read/write register configures the LAN9311/LAN9311i General Purpose Timer (GPT). The GPT can be configured to generate host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the Section 12.1, "General Purpose Timer,"...
Page 268: General Purpose Timer Count Register (Gpt_Cnt)
15:0 General Purpose Timer Current Count (GPT_CNT) This 16-bit field represents the current value of the GPT. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 090h Size: 32 bits General Purpose Timer Configuration Register (GPT_CFG) Section 12.1, "General Purpose Timer,"...
Page 269: Free Running 25Mhz Counter Register (Free_Run)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN) Offset: This read-only register reflects the current value of the free-running 25MHz counter. Refer to 12.2, "Free-Running Clock," on page 162...
Page 270: Reset Control Register (Reset_Ctl)
This register contains software controlled resets. Note: This register can be read while the LAN9311/LAN9311i is in the reset or not ready states. Note: Either half of this register can be read without the need to read the other half.
Page 271: Host Mac Control And Status Registers
MAC address, flow control, multicast hash table, and wake-up configuration. The Host MAC CSR’s also provide serial access to the PHYs via the registers HMAC_MII_ACC and HMAC_MII_DATA. These registers allow access to the 10/100 Ethernet PHY registers and the switch engine (via Port 0). Table 14.6 Host MAC Adressable Registers...
Page 272: Host Mac Control Register (Hmac_Cr)
This read/write register establishes the RX and TX operation modes and controls for address filtering and packet filtering. Refer to Bits 19-15, 13, and 11 determine if the Host MAC accepts the packets from the switch fabric. The switch fabric address table and configuration determine which packets get sent to the Host MAC.
Page 273 9.4.2, "Hash Only Filtering," on page 116 RESERVED Hash/Perfect Filtering Mode (HPFILT) When cleared (0), the LAN9311/LAN9311i will implement a perfect address filter on incoming frames according the address specified in the Host MAC address registers (Host MAC Address High Register (HMAC_ADDRH)
Page 274 When set, the Host MAC’s receiver is enabled and will receive frames. When cleared, the MAC’s receiver is disabled and will not receive any frames. RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION # Bits Used from LFSR Counter DATASHEET Datasheet...
Page 275: Host Mac Address High Register (Hmac_Addrh)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.2 Host MAC Address High Register (HMAC_ADDRH) Offset: This read/write register contains the upper 16-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected.
Page 276: Host Mac Address Low Register (Hmac_Addrl)
EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 32 bits Section 9.6, "Host MAC Address," on page 120 Section 10.2, "I2C/Microwire Master EEPROM Controller,"...
Page 277: Host Mac Multicast Hash Table High Register (Hmac_Hashh)
Hash Table Low register contains the lower 32 bits of the hash table. Refer to Filtering," on page 115 This table determines if the Host MAC accepts the packets from the switch fabric. The switch fabric address table and configuration determine the packets that get sent to the Host MAC.
Page 278: Host Mac Multicast Hash Table Low Register (Hmac_Hashl)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL) Offset: Size: 32 bits This read/write register defines the lower 32-bits of the Multicast Hash Table. Please refer to the...
Page 279: Host Mac Mii Access Register (Hmac_Mii_Acc)
Host MAC MII Data Register The LAN driver software must set this bit in order for the LAN9311/LAN9311i to read or write any of the MII PHY registers. During a MII register access, this bit will be set, signifying a read or write access is in progress.
Page 280: Host Mac Mii Data Register (Hmac_Mii_Data)
This field contains the 16-bit value read from the PHY read operation or the 16-bit data value to be written to the PHY before an MII write operation. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 32 bits...
Page 281: Host Mac Flow Control Register (Hmac_Flow)
System CSR’s to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The Host MAC will not transmit pause frames or assert back pressure if the transmitter is disabled. Note: For the Host MAC, flow control/backpressure is to/from the switch fabric, not the external network. BITS 31:16...
Page 282 Notes: When writing this register, the FCBSY bit must always be zero. Applications must always write a zero to this bit Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet TYPE...
Page 283: Host Mac Vlan1 Tag Register (Hmac_Vlan1)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) Offset: This read/write register contains the VLAN tag field to identify VLAN1 frames. When a VLAN1 frame is detected, the legal frame length is increased from 1518 bytes to 1522 bytes. Refer to "Virtual Local Area Network (VLAN) Support,"...
Page 284: Host Mac Vlan2 Tag Register (Hmac_Vlan2)
If both are set to the same value, VLAN1 is given higher precedence and the maximum legal frame length is set to 1522. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 32 bits for additional information.
Page 285: Host Mac Wake-Up Frame Filter Register (Hmac_Wuff)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF) Offset: This write-only register is used to configure the wake-up frame filter. Refer to Frame Detection," on page 117 BITS...
Page 286: Host Mac Wake-Up Control And Status Register (Hmac_Wucsr)
(HMAC_WUFF). Magic Packet Enable (MPEN) When set, Magic Packet Wake-up mode is enabled. RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: Host MAC Wake-up Frame Filter Register for additional information. DESCRIPTION Host MAC Wake-up...
Page 287: Ethernet Phy Control And Status Registers
This section details the various LAN9311/LAN9311i Ethernet PHY control and status registers. The LAN9311/LAN9311i contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set. All functionality and bit definitions comply with these standards.
Page 288 PHY_SPECIAL_CONTROL_STAT_IND_x PHY_INTERRUPT_SOURCE_x PHY_INTERRUPT_MASK_x PHY_SPECIAL_CONTROL_STATUS_x Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Port x PHY Mode Control/Status Register, Port x PHY Special Modes Register, Port x PHY Special Control/Status Indication Register, Section 14.4.2.10...
Page 289: Port X Phy Basic Control Register (Phy_Basic_Control_X)
1: Reset Loopback (PHY_LOOPBACK) This bit enables/disables the loopback mode. When enabled, transmissions from the switch fabric are not sent to network. Instead, they are looped back into the switch fabric. Note: If loopback is enabled during half-duplex operation, then the...
Page 290 Essentially, if the Auto-Negotiation strap is set, the default value is 0, otherwise the default is determined by the value of the duplex select strap. Refer to Straps," on page 40 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION Auto-Negotiation (PHY_AN) Section 4.2.4, "Configuration Straps," on for more information.
Page 291: Port X Phy Basic Status Register (Phy_Basic_Status_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.2 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) Index (decimal): 1 This register is used to monitor the status of the Port x PHY. BITS 100BASE-T4 This bit displays the status of 100BASE-T4 compatibility.
Page 292 Note 14.52 The PHY supports 100BASE-TX (half and full duplex) and 10BASE-T (half and full duplex) only. All other modes will always return as 0 (unable to perform). Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET...
Page 293: Port X Phy Identification Msb Register (Phy_Id_Msb_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.3 Port x PHY Identification MSB Register (PHY_ID_MSB_x) Index (decimal): 2 This read/write register contains the MSB of the Organizationally Unique Identifier (OUI) for the Port x PHY. The LSB of the PHY OUI is contained in the (PHY_ID_LSB_x).
Page 294: Port X Phy Identification Lsb Register (Phy_Id_Lsb_X)
This field contains the 6-bit manufacturer’s model number of the PHY. Revision Number This field contain the 4-bit manufacturer’s revision number of the PHY. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 16 bits Port x PHY Identification MSB Register...
Page 295: Port X Phy Auto-Negotiation Advertisement Register (Phy_An_Adv_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.5 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) Index (decimal): 4 This read/write register contains the advertised ability of the Port x PHY and is used in the Auto- Negotiation process with the link partner.
Page 296: Table 14.8 10Base-T Full Duplex Advertisement Default Value
Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value autoneg_strap_x speed_strap_x Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION 40. Refer to Section 4.2.4, "Configuration Straps," on page 40 Table 14.8 defines the default behavior of this bit. Configuration 40.
Page 297 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value autoneg_strap_x speed_strap_x Default 10BASE-T Half Duplex (Bit 5) Value SMSC LAN9311/LAN9311i Revision 1.4 (08-19-08) DATASHEET...
Page 298: Port X Phy Auto-Negotiation Link Partner Base Page Ability Register (Phy_An_Lp_Base_Ability_X)
This bit indicates the link partner PHY 100BASE-X half duplex capability. 0: 100BASE-X half duplex ability not supported 1: 100BASE-X half duplex ability supported Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 16 bits DESCRIPTION...
Page 299 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 10BASE-T Full Duplex This bit indicates the link partner PHY 10BASE-T full duplex capability. 0: 10BASE-T full duplex ability not supported 1: 10BASE-T full duplex ability supported 10BASE-T Half Duplex This bit indicates the link partner PHY 10BASE-T half duplex capability.
Page 300: Port X Phy Auto-Negotiation Expansion Register (Phy_An_Exp_X)
This bit indicates the Auto-negotiation ability of the link partner. 0: Link partner is not Auto-Negotiation able 1: Link partner is Auto-Negotiation able Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 16 bits DESCRIPTION...
Page 301: Port X Phy Mode Control/Status Register (Phy_Mode_Control_Status_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.8 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) Index (decimal): 17 This read/write register is used to control and monitor various Port x PHY configuration options. BITS 15:14...
Page 302: Port X Phy Special Modes Register (Phy_Special_Modes_X)
10BASE-T Full Duplex. Auto-negotiation disabled. 100BASE-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: Section 10.2.4, "EEPROM Loader," on page 150 DESCRIPTION Table 14.10...
Page 303 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.10 MODE[2:0] Definitions (continued) MODE[2:0] MODE DEFINITIONS 100BASE-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive. 100BASE-TX Half Duplex is advertised. Auto- negotiation enabled. CRS is active during Transmit & Receive.
Page 304: Port X Phy Special Control/Status Indication Register (Phy_Special_Control_Stat_Ind_X)
Reset Control Register t h e R e s e t ( P H Y _ R S T ) (PHY_BASIC_CONTROL_x) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: DESCRIPTION for configuration strap Table 14.11.
Page 305: Table 14.11Auto-Mdix Enable And Auto-Mdix State Bit Functionality
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.11 Auto-MDIX Enable and Auto-MDIX State Bit Functionality Auto-MDIX Enable Auto-MDIX State (Bit 14) SMSC LAN9311/LAN9311i (Bit 13) Manual mode, no crossover Manual mode, crossover RESERVED (do not use this state)
Page 306: Port X Phy Interrupt Source Flags Register (Phy_Interrupt_Source_X)
INT1 This interrupt source bit indicates an Auto-Negotiation page received. 0: Not source of interrupt 1: Auto-Negotiation page received RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 16 bits (PHY_INTERRUPT_MASK_x). DESCRIPTION DATASHEET...
Page 307: Port X Phy Interrupt Mask Register (Phy_Interrupt_Mask_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) Index (decimal): 30 This read/write register is used to enable or mask the various Port x PHY interrupts and is used in...
Page 308: Port X Phy Special Control/Status Register (Phy_Special_Control_Status_X)
STATE RESERVED 10BASE-T Half-duplex 100BASE-TX Half-duplex RESERVED RESERVED 10BASE-T Full-duplex 100BASE-TX Full-duplex RESERVED RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Size: 16 bits DESCRIPTION DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 0000010b 000b SMSC LAN9311/LAN9311i...
Page 309: Switch Fabric Control And Status Registers
14.5 Switch Fabric Control and Status Registers This section details the various LAN9311/LAN9311i switch control and status registers that reside within the switch fabric. The switch control and status registers allow configuration of each individual switch port, the switch engine, and buffer manager. Switch fabric related interrupts and resets are also controlled and monitored via the switch CSRs.
Page 310 MAC_TX_PKTOK_CNT_MII 0454h MAC_TX_64_CNT_MII Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Port 0 MAC Receive 256 to 511 Byte Count Register, Section 14.5.2.7 Port 0 MAC Receive 512 to 1023 Byte Count Register, Section 14.5.2.8...
Page 311 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0455h MAC_TX_65_TO_127_CNT_MII 0456h MAC_TX_128_TO_255_CNT_MII 0457h MAC_TX_256_TO_511_CNT_MII 0458h MAC_TX_512_TO_1023_CNT_MII 0459h MAC_TX_1024_TO_MAX_CNT_MII 045Ah MAC_TX_UNDSZE_CNT_MII 045Bh RESERVED 045Ch...
Page 312 RESERVED 0851h MAC_TX_DEFER_CNT_1 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Port 1 MAC Receive 65 to 127 Byte Count Register, Section 14.5.2.5 Port 1 MAC Receive 128 to 255 Byte Count Register, Section 14.5.2.6...
Page 313 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0852h MAC_TX_PAUSE_CNT_1 0853h MAC_TX_PKTOK_CNT_1 0854h MAC_RX_64_CNT_1 0855h MAC_TX_65_TO_127_CNT_1 0856h MAC_TX_128_TO_255_CNT_1 0857h MAC_TX_256_TO_511_CNT_1 0858h MAC_TX_512_TO_1023_CNT_1 0859h...
Page 314 0C40h MAC_TX_CFG_2 0C41h MAC_TX_FC_SETTINGS_2 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Port 2 MAC Receive Undersize Count Register, Section 14.5.2.3 Port 2 MAC Receive 64 Byte Count Register, Port 2 MAC Receive 65 to 127 Byte Count Register, Section 14.5.2.5...
Page 315 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0C42h-0C50h RESERVED 0C51h MAC_TX_DEFER_CNT_2 0C52h MAC_TX_PAUSE_CNT_2 0C53h MAC_TX_PKTOK_CNT_2 0C54h MAC_RX_64_CNT_2 0C55h MAC_TX_65_TO_127_CNT_2 0C56h MAC_TX_128_TO_255_CNT_2 0C57h...
Page 316 1845h SWE_PRI_TO_QUE 1846h SWE_PORT_MIRROR Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Switch Engine CSRs Switch Engine ALR Command Register, Switch Engine ALR Write Data 0 Register, Switch Engine ALR Write Data 1 Register,...
Page 317 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 1847h SWE_INGRESS_PORT_TYP 1848h SWE_BCST_THROT 1849h SWE_ADMT_N_MEMBER 184Ah SWE_INGRESS_RATE_CFG 184Bh SWE_INGRESS_RATE_CMD 184Ch SWE_INGRESS_RATE_CMD_STS 184Dh SWE_INGRESS_RATE_WR_DATA 184Eh...
Page 318 1C18h BM_RATE_DRP_CNT_SRC_2 1C19 -1C1F RESERVED Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REGISTER NAME Buffer Manager Flow Control Pause Level Register, Section 14.5.4.3 Buffer Manager Flow Control Resume Level Register, Section 14.5.4.4 Buffer Manager Broadcast Buffer Level Register, Section 14.5.4.5...
Page 319 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 1C20h BM_IMR 1C21h BM_IPR 1C22 -FFFF RESERVED SMSC LAN9311/LAN9311i REGISTER NAME Buffer Manager Interrupt Mask Register,...
Page 320: General Switch Csrs
General Switch CSRs This section details the general switch fabric CSRs. These registers control the main reset and interrupt functions of the switch fabric. A list of the general switch CSRs and their corresponding register numbers is included in 14.5.1.1...
Page 321: Switch Reset Register (Sw_Reset)
This register contains the switch fabric global reset. Refer to more information. BITS 31:1 RESERVED Switch Fabric Reset (SW_RESET) This bit is the global switch fabric reset. All switch fabric blocks are affected. This bit must be manually cleared. SMSC LAN9311/LAN9311i 0001h Size: 32 bits Section 4.2, "Resets,"...
Page 322: Switch Global Interrupt Mask Register (Sw_Imr)
Switch Global Interrupt Mask Register (SW_IMR) Register #: This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch related interrupts in the register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will unmask the interrupt.
Page 323: Switch Global Interrupt Pending Register (Sw_Ipr)
Switch Global Interrupt Pending Register (SW_IPR) Register #: This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related interrupts in this register may be masked via the register.
Page 324: Switch Port 0, Port 1, And Port 2 Csrs
Switch Port 0, Port 1, and Port 2 CSRs This section details the switch Port 0(Host MAC), Port 1, and Port 2 CSRs. Each port provides a functionally identical set of registers which allow for the configuration of port settings, interrupts, and the monitoring of the various packet counters.
Page 325: Port X Mac Receive Configuration Register (Mac_Rx_Cfg_X)
This bit must always be written as 0. RESERVED Enable Receive Own Transmit When set, the switch port will receive its own transmission if it is looped back from the PHY. Normally, this function is only used in Half Duplex PHY loopback.
Page 326: Port X Mac Receive Undersize Count Register (Mac_Rx_Undsze_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 115 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0410h Size: 32 bits Port1: 0810h...
Page 327: Port X Mac Receive 64 Byte Count Register (Mac_Rx_64_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x) Register #: This register provides a counter of 64 byte packets received by the port. The counter is cleared upon being read.
Page 328: Port X Mac Receive 65 To 127 Byte Count Register (Mac_Rx_65_To_127_Cnt_X)
Note: A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0412h Size:...
Page 329: Port X Mac Receive 128 To 255 Byte Count Register (Mac_Rx_128_To_255_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x) Register #: This register provides a counter of received packets between the size of 128 to 255 bytes. The counter is cleared upon being read.
Page 330: Port X Mac Receive 256 To 511 Byte Count Register (Mac_Rx_256_To_511_Cnt_X)
Note: A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0414h Size:...
Page 331: Port X Mac Receive 512 To 1023 Byte Count Register (Mac_Rx_512_To_1023_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x) Register #: This register provides a counter of received packets between the size of 512 to 1023 bytes. The counter is cleared upon being read.
Page 332: Port X Mac Receive 1024 To Max Byte Count Register (Mac_Rx_1024_To_Max_Cnt_X)
(e.g. a 1518 1/2 byte packet) is counted. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0416h Size: 32 bits...
Page 333: Port X Mac Receive Oversize Count Register (Mac_Rx_Ovrsze_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) Register #: This register provides a counter of received packets with a size greater than the maximum byte size.
Page 334: Port X Mac Receive Ok Count Register (Mac_Rx_Pktok_Cnt_X)
Minimum rollover time at 100Mbps is approximately 481 hours. Note: A bad packet is one that has a FCS or Symbol error. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0418h Size: 32 bits...
Page 335: Port X Mac Receive Crc Error Count Register (Mac_Rx_Crcerr_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x) Register #: This register provides a counter of received packets that with CRC errors. The counter is cleared upon being read.
Page 336: Port X Mac Receive Multicast Count Register (Mac_Rx_Mulcst_Cnt_X)
Minimum rollover time at 100Mbps is approximately 481 hours. Note: A bad packet is one that has a FCS or Symbol error. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 041Ah Size: 32 bits...
Page 337: Port X Mac Receive Broadcast Count Register (Mac_Rx_Brdcst_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) Register #: This register provides a counter of valid received packets with a broadcast destination address. The counter is cleared upon being read.
Page 338: Port X Mac Receive Pause Frame Count Register (Mac_Rx_Pause_Cnt_X)
Minimum rollover time at 100Mbps is approximately 481 hours. Note: A bad packet is one that has a FCS or Symbol error. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 041Ch Size: 32 bits...
Page 339: Port X Mac Receive Fragment Error Count Register (Mac_Rx_Frag_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x) Register #: This register provides a counter of received packets of less than 64 bytes and a FCS error. The counter is cleared upon being read.
Page 340: Port X Mac Receive Jabber Error Count Register (Mac_Rx_Jabb_Cnt_X)
(e.g. a 1518 1/2 byte packet) and contains a FCS error is not considered jabber and is not counted here. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 041Eh Size: 32 bits...
Page 341: Port X Mac Receive Alignment Error Count Register (Mac_Rx_Align_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) Register #: This register provides a counter of received packets with 64 bytes to the maximum allowable, and a FCS error.
Page 342: Port X Mac Receive Packet Length Count Register (Mac_Rx_Pktlen_Cnt_X)
Note: A bad packet is one that has an FCS or Symbol error. For this counter, a packet that is not an integral number of bytes (e.g. a 1518 1/2 byte packet) is rounded down to the nearest byte. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0420h Size:...
Page 343: Port X Mac Receive Good Packet Length Count Register (Mac_Rx_Goodpktlen_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) Register #: This register provides a counter of total bytes received in good packets. The counter is cleared upon being read.
Page 344: Port X Mac Receive Symbol Error Count Register (Mac_Rx_Symbol_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 115 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0422h Size: 32 bits Port1: 0822h...
Page 345: Port X Mac Receive Control Frame Count Register (Mac_Rx_Ctlfrm_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) Register #: This register provides a counter of good packets with a type field of 8808h. The counter is cleared upon being read.
Page 346: Port X Mac Transmit Configuration Register (Mac_Tx_Cfg_X)
TX Enable When set, the transmit port is enabled. When cleared, the transmit port is disabled. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0440h Size: 32 bits Port1: 0840h Port2: 0C40h...
Page 347: Port X Mac Transmit Flow Control Settings Register (Mac_Tx_Fc_Settings_X)
01 = Reset on successful reception 1X = Reset on either successful transmission or reception 15:0 Pause Time Value The value that is inserted into the transmitted pause packet when the switch wants to “XOFF” its link partner. SMSC LAN9311/LAN9311i Port0: 0441h...
Page 348: Port X Mac Transmit Deferred Count Register (Mac_Tx_Defer_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0451h Size: 32 bits Port1: 0851h...
Page 349: Port X Mac Transmit Pause Count Register (Mac_Tx_Pause_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) Register #: This register provides a counter of transmitted pause packets. The counter is cleared upon being read. BITS...
Page 350: Port X Mac Transmit Ok Count Register (Mac_Tx_Pktok_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0453h Size: 32 bits Port1: 0853h...
Page 351: Port X Mac Transmit 64 Byte Count Register (Mac_Tx_64_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) Register #: This register provides a counter of 64 byte packets transmitted by the port. The counter is cleared upon being read.
Page 352: Port X Mac Transmit 65 To 127 Byte Count Register (Mac_Tx_65_To_127_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 487 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0455h Size: 32 bits Port1: 0855h...
Page 353: Port X Mac Transmit 128 To 255 Byte Count Register (Mac_Tx_128_To_255_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) Register #: This register provides a counter of transmitted packets between the size of 128 to 255 bytes. The counter is cleared upon being read.
Page 354: Port X Mac Transmit 256 To 511 Byte Count Register (Mac_Tx_256_To_511_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 1581 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0457h Size: 32 bits Port1: 0857h...
Page 355: Port X Mac Transmit 512 To 1023 Byte Count Register (Mac_Tx_512_To_1023_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) Register #: This register provides a counter of transmitted packets between the size of 512 to 1023 bytes. The counter is cleared upon being read.
Page 356: Port X Mac Transmit 1024 To Max Byte Count Register (Mac_Tx_1024_To_Max_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 5979 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0459h Size: 32 bits Port1: 0859h...
Page 357: Port X Mac Transmit Undersize Count Register (Mac_Tx_Undsze_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) Register #: This register provides a counter of undersized packets transmitted by the port. The counter is cleared upon being read.
Page 358: Port X Mac Transmit Packet Length Count Register (Mac_Tx_Pktlen_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 5.8 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 045Ch Size: 32 bits Port1: 085Ch...
Page 359: Port X Mac Transmit Broadcast Count Register (Mac_Tx_Brdcst_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) Register #: This register provides a counter of transmitted broadcast packets. The counter is cleared upon being read. BITS...
Page 360: Port X Mac Transmit Multicast Count Register (Mac_Tx_Mulcst_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 045Eh Size: 32 bits Port1: 085Eh...
Page 361: Port X Mac Transmit Late Collision Count Register (Mac_Tx_Latecol_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) Register #: This register provides a counter of transmitted packets which experienced a late collision. The counter is cleared upon being read.
Page 362: Port X Mac Transmit Excessive Collision Count Register (Mac_Tx_Exccol_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 1466 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0460h Size: 32 bits Port1: 0860h...
Page 363: Port X Mac Transmit Single Collision Count Register (Mac_Tx_Snglecol_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) Register #: This register provides a counter of transmitted packets which experienced exactly 1 collision. The counter is cleared upon being read.
Page 364: Port X Mac Transmit Multiple Collision Count Register (Mac_Tx_Multicol_Cnt_X)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 664 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0462h Size: 32 bits Port1: 0862h...
Page 365: Port X Mac Transmit Total Collision Count Register (Mac_Tx_Totalcol_Cnt_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x) Register #: This register provides a counter of total collisions including late collisions. The counter is cleared upon being read.
Page 366: Port X Mac Interrupt Mask Register (Mac_Imr_X)
RESERVED RESERVED Note: These bits must be written as 11h Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Port0: 0480h Size: Port1: 0880h Port2: 0C80h may be masked via this register. An interrupt is masked by setting the for more information.
Page 367: Port X Mac Interrupt Pending Register (Mac_Ipr_X)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) Register #: This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been triggered. All interrupts in this register may be masked via the (MAC_IPR_x) register.
Page 368: Switch Engine Csrs
This section details the switch engine related CSRs. These registers allow configuration and monitoring of the various switch engine components including the ALR, VLAN, Port VID, and DIFFSERV tables. A list of the general switch CSRs and their corresponding register numbers is included in 14.5.3.1...
Page 369: Switch Engine Alr Write Data 0 Register (Swe_Alr_Wr_Dat_0)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) Register #: This register is used in conjunction with the (SWE_ALR_WR_DAT_1) Entry command in the BITS 31:0 MAC Address This field contains the first 32 bits of the ALR entry that will be written into the ALR table.
Page 370: Switch Engine Alr Write Data 1 Register (Swe_Alr_Wr_Dat_1)
Static bit of this register is set, and the DA Highest Priority (bit 5) in the Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG) Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1802h Size: Switch Engine ALR Write Data 0 Register...
Page 371 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS 18:16 Port These bits indicate the port(s) associated with this MAC address. When bit 18 is cleared, a single port is selected. When bit 18 is set, multiple ports are selected.
Page 372: Switch Engine Alr Read Data 0 Register (Swe_Alr_Rd_Dat_0)
32 bits of the MAC address. Bit 0 holds the LSB of the first byte (the multicast bit). Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1805h Size: Switch Engine ALR Read Data 1 Register to read the ALR table.
Page 373: Switch Engine Alr Read Data 1 Register (Swe_Alr_Rd_Dat_1)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) Register #: This register is used in conjunction with the (SWE_ALR_RD_DAT_0) loaded via the Get First Entry or Get Next Entry commands in the Register (SWE_ALR_CMD).
Page 374 (the last bit on the wire). The first 32 bits of the MAC address are located in the Switch Engine ALR Read Data 0 Register Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION ASSOCIATED PORT(S) Port 0(Host MAC)
Page 375: Switch Engine Alr Command Status Register (Swe_Alr_Cmd_Sts)
When set, indicates that the Make Entry command is taking place. This bit is cleared once the Make Entry command has finished. Note 14.62 The default value of this bit is 0 immediately following any switch fabric reset and then self- sets to 1 once the ALR table is initialized.
Page 376: Switch Engine Alr Configuration Register (Swe_Alr_Cfg)
BITS 31:1 RESERVED ALR Age Test When set, this bit decreases the aging timer from 5 minutes to 50mS. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1809h Size: 32 bits DESCRIPTION DATASHEET Datasheet...
Page 377: Switch Engine Vlan Command Register (Swe_Vlan_Cmd)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD) Register #: This register is used to read and write the VLAN or Port VID tables. A write to this address performs the specified access.
Page 378: Switch Engine Vlan Write Data Register (Swe_Vlan_Wr_Data)
VLAN entry. Note: A value of 3FFh is considered reserved by IEEE 802.1Q and should not be used. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 180Ch Size: DESCRIPTION Switch Engine (SWE_VLAN_CMD)), bits 11:0 of this field specify...
Page 379: Switch Engine Vlan Read Data Register (Swe_Vlan_Rd_Data)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) Register #: This register is used to read the VLAN or Port VID tables. BITS 31:18 RESERVED 17:0 Port Default VID and Priority...
Page 380: Switch Engine Vlan Command Status Register (Swe_Vlan_Cmd_Sts)
When set, this bit indicates that the read or write command is taking place. This bit is cleared once the command has finished. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1810h Size: 32 bits...
Page 381: Switch Engine Diffserv Table Command Register (Swe_Diffserv_Tbl_Cfg)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG) Register #: This register is used to read and write the DIFFSERV table. A write to this address performs the specified access.
Page 382: Switch Engine Diffserv Table Write Data Register (Swe_Diffserv_Tbl_Wr_Data)
RESERVED DIFFSERV Priority These bits specify the assigned receive priority for IP packets with a ToS/CS field that matches this index. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1812h Size: 32 bits DESCRIPTION...
Page 383: Switch Engine Diffserv Table Read Data Register (Swe_Diffserv_Tbl_Rd_Data)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) Register #: This register is used to read the DIFFSERV table. BITS 31:3 RESERVED DIFFSERV Priority These bits specify the assigned receive priority for IP packets with a ToS/CS field that matches this index.
Page 384: Switch Engine Diffserv Table Command Status Register (Swe_Diffserv_Tbl_Cmd_Sts)
When set, this bit indicates that the read or write command is taking place. This bit is cleared once the command has finished. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1814h Size: 32 bits...
Page 385: Switch Engine Global Ingress Configuration Register (Swe_Global_Ingrss_Cfg)
When set, IPv4 IGMP packets are snooped and sent to the MLD/IGMP snoop port. SWE Counter Test When this bit is set the Switch Engine counters that normally clear to 0 when read will be set to 7FFF_FFFCh when read. DA Highest Priority...
Page 386 VLAN Enable When set, VLAN ingress rules are enabled. This also enables the VLAN to be used as the transmit priority queue selection. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet...
Page 387: Switch Engine Port Ingress Configuration Register (Swe_Port_Ingrss_Cfg)
When set, source addresses are learned when a packet is received on the corresponding port and the corresponding Port State in the Port State Register (SWE_PORT_STATE) There is one enable bit per ingress port. Bits 5,4,3 correspond to switch ports 2,1,0 respectively. Enable Membership Checking When set, VLAN membership is checked when a packet is received on the corresponding port.
Page 388: Switch Engine Admit Only Vlan Register (Swe_Admt_Only_Vlan)
The VLAN Enable bit in the Register (SWE_GLOBAL_INGRSS_CFG) have an affect. There is one enable bit per ingress port. Bits 2,1,0 correspond to switch ports 2,1,0 respectively. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface...
Page 389: Switch Engine Port State Register (Swe_Port_State)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.19 Switch Engine Port State Register (SWE_PORT_STATE) Register #: This register is used to configure the per port spanning tree state. BITS 31:6 RESERVED Port State Port 2 These bits specify the spanning tree port states for Port 2.
Page 390: Switch Engine Priority To Queue Register (Swe_Pri_To_Que)
1. Priority 0 traffic Class These bits specify the egress queue that is used for packets with a priority of 0. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1845h Size: 32 bits DESCRIPTION...
Page 391: Switch Engine Port Mirroring Register (Swe_Port_Mirror)
Bits 7,6,5 correspond to switch ports 2,1,0 respectively. Note: Only one port should be set as the sniffer. Mirrored Port These bits specify if a port is to be mirrored. Bits 4,3,2 correspond to switch ports 2,1,0 respectively. Note: Multiple ports can be set as mirrored.
Page 392: Switch Engine Ingress Port Type Register (Swe_Ingrss_Port_Typ)
A setting of 11b enables the usage of the VLAN tag to specify the packet destination. All other values disable this feature. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1847h Size: 32 bits...
Page 393: Switch Engine Broadcast Throttling Register (Swe_Bcst_Throt)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.23 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) Register #: This register configures the broadcast input rate throttling. BITS 31:27 RESERVED Broadcast Throttle Enable Port 2 This bit enables broadcast input rate throttling on Port 2.
Page 394: Switch Engine Admit Non Member Register (Swe_Admt_N_Member)
When set, a received packet is accepted even if the ingress port is not a member of the destination VLAN. The VLAN still must be active in the switch. There is one bit per ingress port. Bits 2,1,0 correspond to switch ports 2,1,0 respectively. Revision 1.4 (08-19-08)
Page 395: Switch Engine Ingress Rate Configuration Register (Swe_Ingrss_Rate_Cfg)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.25 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) Register #: This register, along with the settings accessible via the (SWE_INGRSS_RATE_CMD), is used to configure the ingress rate metering/coloring.
Page 396: Switch Engine Ingress Rate Command Register (Swe_Ingrss_Rate_Cmd)
23. Note: Values outside of the valid range may cause unexpected results. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 184Bh Size: 32 bits Switch Engine Ingress Rate Command Status indicates when the command is finished.
Page 397: 26.1Ingress Rate Table Registers
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.26.1 INGRESS RATE TABLE REGISTERS The ingress rate metering/color table consists of 24 Committed Information Rate (CIR) registers (one per port/priority), a Committed Burst Size register, and an Excess Burst Size register. All metering/color...
Page 398: Switch Engine Ingress Rate Command Status Register (Swe_Ingrss_Rate_Cmd_Sts)
Operation Pending When set, indicates that the read or write command is taking place. This bit is cleared once the command has finished. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 184Ch Size: 32 bits...
Page 399: Switch Engine Ingress Rate Write Data Register (Swe_Ingrss_Rate_Wr_Data)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.28 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA) Register #: This register is used to write the ingress rate table registers. BITS 31:16 RESERVED 15:0 Data This is the data to be written to the ingress rate table registers as specified...
Page 400: Switch Engine Ingress Rate Read Data Register (Swe_Ingrss_Rate_Rd_Data)
This is the read data from the ingress rate table registers as specified in the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD). Refer to Table Registers," on page 397 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 184Eh Size: 32 bits DESCRIPTION Section 14.5.3.26.1, "Ingress Rate...
Page 401: Switch Engine Port 0 Ingress Filtered Count Register (Swe_Filtered_Cnt_Mii)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.30 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII) Register #: This register counts the number of packets filtered at ingress on Port 0(Host MAC). This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
Page 402: Switch Engine Port 1 Ingress Filtered Count Register (Swe_Filtered_Cnt_1)
This field is a count of packets filtered at ingress and is cleared when read. Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1851h Size: 32 bits DESCRIPTION...
Page 403: Switch Engine Port 2 Ingress Filtered Count Register (Swe_Filtered_Cnt_2)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) Register #: This register counts the number of packets filtered at ingress on Port 2. This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
Page 404: Switch Engine Port 0 Ingress Vlan Priority Regeneration Table Register (Swe_Ingrss_Regen_Tbl_Mii)
These bits specify the regenerated priority for received priority 1. Regen0 These bits specify the regenerated priority for received priority 0. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1855h Size: 32 bits DESCRIPTION...
Page 405: Switch Engine Port 1 Ingress Vlan Priority Regeneration Table Register (Swe_Ingrss_Regen_Tbl_1)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) Register #: This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is used in determining the output priority queue.
Page 406: Switch Engine Port 2 Ingress Vlan Priority Regeneration Table Register (Swe_Ingrss_Regen_Tbl_2)
These bits specify the regenerated priority for received priority 1. Regen0 These bits specify the regenerated priority for received priority 0. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1857h Size: 32 bits DESCRIPTION...
Page 407: Switch Engine Port 0 Learn Discard Count Register (Swe_Lrn_Discrd_Cnt_Mii)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.36 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII) Register #: This register counts the number of MAC addresses on Port 0(Host MAC) that were not learned or were overwritten by a different address due to address table space limitations.
Page 408: Switch Engine Port 1 Learn Discard Count Register (Swe_Lrn_Discrd_Cnt_1)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1859h Size: 32 bits DESCRIPTION...
Page 409: Switch Engine Port 2 Learn Discard Count Register (Swe_Lrn_Discrd_Cnt_2)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.3.38 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) Register #: This register counts the number of MAC addresses on Port 2 that were not learned or were overwritten by a different address due to address table space limitations.
Page 410: Switch Engine Interrupt Mask Register (Swe_Imr)
14.5.3.39 Switch Engine Interrupt Mask Register (SWE_IMR) Register #: This register contains the Switch Engine interrupt mask, which masks the interrupts in the Engine Interrupt Pending Register Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to on page 49 for more information.
Page 411: Switch Engine Interrupt Pending Register (Swe_Ipr)
14.5.3.40 Switch Engine Interrupt Pending Register (SWE_IPR) Register #: This register contains the Switch Engine interrupt status. The status is double buffered. All interrupts in this register may be masked via the Refer to Chapter 5, "System Interrupts," on page 49...
Page 412 11 = RESERVED Set A Valid When set, bits 7:2 are valid. Interrupt Pending When set, a packet dropped event(s) is indicated. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet TYPE DEFAULT...
Page 413: Buffer Manager Csrs
Buffer Manager CSRs This section details the Buffer Manager (BM) registers. These registers allow configuration and monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their corresponding register numbers is included in 14.5.4.1...
Page 414: Buffer Manager Drop Level Register (Bm_Drop_Lvl)
1 port is active. Each buffer is 128 bytes. Note: A port is “active” when 36 buffers are in use for that port. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C01h Size: 32 bits DESCRIPTION...
Page 415: Buffer Manager Flow Control Pause Level Register (Bm_Fc_Pause_Lvl)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL) Register #: This register configures the buffer usage level when a Pause frame or backpressure is sent. BITS 31:16...
Page 416: Buffer Manager Flow Control Resume Level Register (Bm_Fc_Resume_Lvl)
Each buffer is 128 bytes. Note: A port is “active” when 36 buffers are in use for that port. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C03h Size: 32 bits DESCRIPTION DATASHEET...
Page 417: Buffer Manager Broadcast Buffer Level Register (Bm_Bcst_Lvl)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.5 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL) Register #: This register configures the buffer usage limits for broadcasts, multicasts, and unknown unicasts. BITS 31:8 RESERVED Broadcast Drop Level These bits specify the maximum number of buffers that can be used by broadcasts, multicasts, and unknown unicasts.
Page 418: Buffer Manager Port 0 Drop Count Register (Bm_Drp_Cnt_Src_Mii)
Note: The counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C05h Size: 32 bits DESCRIPTION...
Page 419: Buffer Manager Port 1 Drop Count Register (Bm_Drp_Cnt_Src_1)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) Register #: This register counts the number of packets dropped by the Buffer Manager that were received on Port 1.
Page 420: Buffer Manager Port 2 Drop Count Register (Bm_Drp_Cnt_Src_2)
Note: The counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C07h Size: 32 bits DESCRIPTION...
Page 421: Buffer Manager Reset Status Register (Bm_Rst_Sts)
The initialization is performed upon any reset that resets the switch fabric. Note 14.63 The default value of this bit is 0 immediately following any switch fabric reset and then self- sets to 1 once the ALR table is initialized.
Page 422: Buffer Manager Random Discard Table Command Register (Bm_Rndm_Dscrd_Tbl_Cmd)
1011 1100 1101 1110 1111 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C09h Size: 32 bits Buffer Manager Random Discard Table Read Data Register can be read following a write to this register.
Page 423: Buffer Manager Random Discard Table Write Data Register (Bm_Rndm_Dscrd_Tbl_Wdata)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.11 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) Register #: This register is used to write the Random Discard Weight table. Note: The Random Discard Weight table is not initialized upon reset or power-up. If a random discard is enabled, the full table should be initialized by the host.
Page 424: Buffer Manager Random Discard Table Read Data Register (Bm_Rndm_Dscrd_Tbl_Rdata)
14.5.4.10, "Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD)". Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C0Bh Size: 32 bits...
Page 425: Buffer Manager Egress Port Type Register (Bm_Egrss_Port_Type)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) Register #: This register is used to configure the egress VLAN tagging rules. See Removing, and Changing VLAN Tags," on page 79...
Page 426 Identical to Change Tag Port 2 definition above. Egress Port Type Port 0(Host MAC) Identical to Egress Port Type Port 2 definition above. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface DESCRIPTION EGRESS PORT TYPE Section 6.5.6, for additional Section 6.5.6,...
Page 427: Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (Bm_Egrss_Rate_00_01)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.14 Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01) Register #: This register, along with the the egress rate pacing. BITS 31:26 RESERVED 25:13 Egress Rate Port 0 Priority Queue 1 These bits specify the egress data rate for the Port 0(Host MAC) priority queue 1.
Page 428: Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (Bm_Egrss_Rate_02_03)
These bits specify the egress data rate for the Port 0(Host MAC) priority queue 2. The rate is specified in time per byte. The time is this value plus 1 times 20nS. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C0Eh Size: 32 bits...
Page 429: Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (Bm_Egrss_Rate_10_11)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.16 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11) Register #: This register, along with the the egress rate pacing. BITS 31:26 RESERVED 25:13 Egress Rate Port 1 Priority Queue 1 These bits specify the egress data rate for the Port 1 priority queue 1.
Page 430: Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (Bm_Egrss_Rate_12_13)
These bits specify the egress data rate for the Port 1 priority queue 2. The rate is specified in time per byte. The time is this value plus 1 times 20nS. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C10h Size:...
Page 431: Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (Bm_Egrss_Rate_20_21)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.18 Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21) Register #: This register, along with the the egress rate pacing. BITS 31:26 RESERVED 25:13 Egress Rate Port 2 Priority Queue 1 These bits specify the egress data rate for the Port 2 priority queue 1.
Page 432: Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (Bm_Egrss_Rate_22_23)
These bits specify the egress data rate for the Port 2 priority queue 2. The rate is specified in time per byte. The time is this value plus 1 times 20nS. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C12h Size:...
Page 433: Buffer Manager Port 0 Default Vlan Id And Priority Register (Bm_Vlan_Mii)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII) Register #: This register is used to specify the default VLAN ID and priority of Port 0(Host MAC).
Page 434: Buffer Manager Port 1 Default Vlan Id And Priority Register (Bm_Vlan_1)
11:0 Default VLAN ID These bits specify the default that is used when a tag is inserted or changed on egress. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C14h Size: 32 bits DESCRIPTION...
Page 435: Buffer Manager Port 2 Default Vlan Id And Priority Register (Bm_Vlan_2)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) Register #: This register is used to specify the default VLAN ID and priority of Port 2.
Page 436: Buffer Manager Port 0 Ingress Rate Drop Count Register (Bm_Rate_Drp_Cnt_Src_Mii)
MAC) and is cleared when read. Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C16h Size: 32 bits DESCRIPTION...
Page 437: Buffer Manager Port 1 Ingress Rate Drop Count Register (Bm_Rate_Drp_Cnt_Src_1)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.24 Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) Register #: This register counts the number of packets received on Port 1 that were dropped by the Buffer Manager due to ingress rate limit discarding (Red and random Yellow dropping).
Page 438: Buffer Manager Port 2 Ingress Rate Drop Count Register (Bm_Rate_Drp_Cnt_Src_2)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C18h Size: 32 bits DESCRIPTION...
Page 439: Buffer Manager Interrupt Mask Register (Bm_Imr)
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 14.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR) Register #: This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Manager Interrupt Pending Register the Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to Interrupts,"...
Page 440: Buffer Manager Interrupt Pending Register (Bm_Ipr)
10 = Port 2 11 = RESERVED Status B Pending When set, bits 13:8 are valid. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface 1C21h Size: 32 bits Buffer Manager Interrupt Mask Register (BM_IMR) for more information.
Page 441 Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet BITS Drop Reason A When bit 0 is set, these bits indicate the reason a packet was dropped. See the Drop Reason B description above for definitions of each value of this field.
Page 442: Chapter 15 Operational Characteristics
Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO)....+3.3V +/- 300mV Ambient Operating Temperature in Still Air (T **Proper operation of the LAN9311/LAN9311i is guaranteed only within the ranges specified in this section.
Page 443: Power Consumption
15.3 Power Consumption This section details the power consumption of the LAN9311/LAN9311i. Power consumption values are provided for both the device-only, and for the device plus the Ethernet components on ports 1 and 2. Table 15.1 Supply and Current (10BASE-T Full-Duplex) PARAMETER Supply current at 3.3V...
Page 444: Dc Specifications
Peak Differential Output Voltage Low Signal Amplitude Symmetry Signal Rise and Fall Time Rise and Fall Symmetry Duty Cycle Distortion Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 15.3 I/O Buffer Characteristics -0.3 1.01 1.18 1.35 1.39...
Page 445: Ac Specifications
Note 15.11 Min/max voltages guaranteed as measured with 100 Ω resistive load. 15.5 AC Specifications This section details the various AC timing specifications of the LAN9311/LAN9311i. Note: The I C timing adheres to the Philips I Specification for detailed I 15.5.1...
Page 446: Reset And Configuration Strap Timing
Note: Device configuration straps are latched as a result of nRST assertion. Refer to "Configuration Straps," on page 40 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Section 4.2, "Resets," on page 36 rstia odad Figure 15.2 nRST Reset Pin Timing...
Page 447: Power-On Configuration Strap Valid Timing
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.3 Power-On Configuration Strap Valid Timing This diagram illustrates the configuration strap valid timing requirements in relation to power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met.
Page 448: Pio Read Cycle Timing
These signals may be asserted and de-asserted in any order. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface for a functional description of this mode. cycle csdv Figure 15.4 PIO Read Cycle Timing...
Page 449: Pio Burst Read Cycle Timing
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.5 PIO Burst Read Cycle Timing Please refer to Section 8.5.5, "PIO Burst Reads," on page 108 A[x:5], END_SEL A[4:1] nCS, nRD D[15:0] Figure 15.5 PIO Burst Read Cycle Timing Table 15.9 PIO Burst Read Cycle Timing Values...
Page 450: Rx Data Fifo Direct Pio Read Cycle Timing
Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de- asserted in any order. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface cycle csdv DESCRIPTION...
Page 451: Rx Data Fifo Direct Pio Burst Read Cycle Timing
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing Please refer to Section 8.5.7, "RX Data FIFO Direct PIO Burst Reads," on page 110 description of this mode.
Page 452: Pio Write Cycle Timing
These signals may be asserted and de-asserted in any order. Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface for a functional description of this mode. cycle Figure 15.8 PIO Write Cycle Timing...
Page 453: Tx Data Fifo Direct Pio Write Cycle Timing
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing Please refer to Section 8.5.9, "TX Data FIFO Direct PIO Writes," on page 112 description of this mode. FIFO_SEL...
Page 454: Microwire Timing
EEDI valid after EECS high (VERIFY) cshdv EEDI hold after EECS low (VERIFY) dhcsl EECS low Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface for a functional description of this serial interface. ckcyc dvckh ckhdis dsckh...
Page 455: Clock Circuit
15.6 Clock Circuit The LAN9311/LAN9311i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
Page 456: Chapter 16 Package Outlines
D1/E1 13.80 14.00 0.45 0.60 0.13 0.18 0.09 0.40 BSC 0.00 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface REMARKS 1.20 Overall Package Height 0.15 Standoff 1.05 Body Thickness 16.20 X/Y Span 14.20 X/Y Plastic Body Size 0.75...
Page 457: Figure 16.2 Lan9311 128-Vtqfp Recommended Pcb Land Pattern
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. Dimensions b & c apply to the flat section of the lead foot between 0.10 and 0.25mm from the lead tip. The base metal is exposed at the lead tip.
Page 458: 128-Xvtqfp Package Outline
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Datasheet 16.2 128-XVTQFP Package Outline Figure 16.3 LAN9311/LAN9311i 128-XVTQFP Package Definition Revision 1.4 (08-19-08) SMSC LAN9311/LAN9311i DATASHEET...
Page 459: Figure 16.4 Lan9311/Lan9311I 128-Xvtqfp Recommended Pcb Land Pattern
4. Dimensions D2 and E2 represent the size of the exposed pad. The exposed pad shall be coplanar with the bottom of the package within 0.05mm. 5. The pin 1 identifier may vary, but is always located within the zone indicated Figure 16.4 LAN9311/LAN9311i 128-XVTQFP Recommended PCB Land Pattern SMSC LAN9311/LAN9311i REMARKS 1.20...
Page 460: Chapter 17 Revision History
Section 15.6, "Clock Circuit," on page 455 Revision 1.4 (08-19-08) Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface Table 17.1 Customer Revision History Added note at end of WUFF section and to the BCAST bit of the MAC_CR register stating:...

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Lan9311

SMSC LAN9311i Datasheet

Chapter 1 Preface

Chapter 2 Introduction

Chapter 3 Pin Description and Configuration

Chapter 4 Clocking, Resets, and Power Management

Chapter 5 System Interrupts

Chapter 6 Switch Fabric

Chapter 7 Ethernet Phys

Chapter 8 Host Bus Interface (HBI)

Chapter 9 Host MAC

Chapter 10 Serial Management

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Summary of Contents for SMSC LAN9311i