Realtek RTL8201(L) Manual

Single chip port 10/100mbps fast ethernet phyceiver

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SINGLE PORT 10/100MBPS
FAST ETHERNET PHYCEIVER
1. Features........................................................................ 2
2. General Description .................................................... 2
3. Block Diagram............................................................. 3
4. Pin Assignments .......................................................... 4
5. Pin Description ............................................................ 5
5.1 100 Mbps MII & PCS Interface ............................. 5
5.2 Serial Network Interface (SNI) .............................. 5
5.3 Clock Interface ....................................................... 5
5.4 100Mbps Network Interface................................... 6
5.5 Device Configuration Interface .............................. 6
5.6 LED Interface/PHY Address Config...................... 6
5.7 Reset and Test pins................................................. 6
5.8 Power and Ground pins .......................................... 6
6. Register Descriptions .................................................. 7
6.1 Register 0 Basic Mode Control .............................. 7
6.2 Register 1 Basic Mode Status................................. 9
6.3. Register 2 PHY Identifier 1................................. 10
6.4. Register 3 PHY Identifier 2................................. 10
6.8 Register 16 Nway Setup (NSR)....................................... 14
6.12 Register 20 PHY 1_1.......................................... 15
6.13 Register 21 PHY 1_2.......................................... 16
2002-01-18
Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL:
REALTEK SINGLE CHIP
RTL8201(L)
6.13 Register 22 PHY 2 ............................................. 16
6.14 Register 23 Twister_1 ........................................ 16
6.15 Register 24 Twister_2 ........................................ 16
7. Functional Description ............................................. 17
7.1 MII and Management Interface............................ 17
7.3 Flow control support ............................................ 18
7.6 Serial Network Interface ...................................... 20
7.8 Media Interface .................................................... 21
7.8.1 100Base Tx/Rx ............................................. 21
7.8.2 10Base Tx/Rx ............................................... 22
7.9 Repeater Mode Operation .................................... 22
7.10 Reset, Power, and Transmit Bias........................ 22
8. Electrical Characteristics ......................................... 23
8.1 D.C. Characteristics ............................................. 23
8.1.1. Absolute Maximum Ratings ........................ 23
8.1.2. Operating Conditions................................... 23
8.1.3. Power Dissipation........................................ 23
8.1.4 Supply Voltage: Vcc ..................................... 23
8.2 A.C. Characteristics ............................................. 24
8.2.2 Reception Without Error............................... 24
9. Mechanical Dimensions ............................................ 25
1
info@cornelius-consult.de
RTL8201(L)
Rev.1.04
http://www.cornelius-consult.de

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Summary of Contents for Realtek RTL8201(L)

  • Page 1: Table Of Contents

    RTL8201(L) REALTEK SINGLE CHIP SINGLE PORT 10/100MBPS FAST ETHERNET PHYCEIVER RTL8201(L) 6.13 Register 22 PHY 2 ..........16 1. Features................ 2 2. General Description ............ 2 6.14 Register 23 Twister_1 ........16 3. Block Diagram............. 3 6.15 Register 24 Twister_2 ........16 4.
  • Page 2: Features

    RTL8201(L) 1. Features The Realtek RTL8201(L) is a Fast Ethernet Phyceiver with MII interface to the MAC chip. It provides the following features: Supports MII interface 3.3V operation with 5V signal tolerance Supports 10/100Mbps operation Low operation power consumption Supports half/full duplex operation Adaptive Equalization IEEE 802.3/802.3u compliant...
  • Page 3: Block Diagram

    RTL8201(L) 3. Block Diagram 100M Data Descrambler RXC 25M Decoder Alignment Interface 10/100 half/full Switch Logic Scrambler TXC 25M Encoder Interface 10/100M Auto-negotiation Control Logic Link pulse TXC10 Manchester coded 10M Output waveform TXD10 waveform shaping RXC10 RXD10 Data Recovery Receive low pass filter TXC 25M TXO+...
  • Page 4: Pin Assignments

    RTL8201(L) 4. Pin Assignments 37. ANE 24. RXER 38. Duplex 23. CRS 39. Speed 22. RXDV 40. RPTR/ 21. RXD0 RTT2 41. LDPS 20. RXD1 42. RESETB 19. RXD2 RTL8201 43. ISOLATE 18. RXD3 44. MII/ 17. DGND SNIB 45. AGND 16.
  • Page 5: Pin Description

    RTL8201(L) 5. Pin Description 5.1 100 Mbps MII & PCS Interface Symbol Type Pin(s) No. Description Transmit Clock: This pin provides a continuous clock as a timing reference for TXD[3:0] and TXEN. TXEN Transmit Enable: The input signal indicates the presence of a valid nibble data on TXD[3:0].
  • Page 6: 100Mbps Network Interface

    RTL8201(L) 5.4 100Mbps Network Interface Symbol Type Pin(s) No. Description TPTX+ Transmit Output TPTX- RTSET Transmit bias resistor connection: This pin should be pulled to GND by a 2.0K resistor. TPRX+ Receive input TPRX- 5.5 Device Configuration Interface Symbol Type Pin(s) No.
  • Page 7: Register Descriptions

    This section will describe definitions and usage for each of the registers available in the RTL8201. The first six registers of the MII are defined by the MII specification. Other registers are defined by Realtek Semiconductor Corp. for internal use and are reserved for specific uses.
  • Page 8 RTL8201(L) 0:<12> Auto Auto Negotiation Enable: Auto-negotiation can be disabled by either 1, RW Negotiation hardware or software control. This bit can enable/disable the Nway Enable auto-negotiation function. If the ANEN input pin is driven to a logic ‘0’, Auto-negotiation disabled software control.
  • Page 9: Register 1 Basic Mode Status

    RTL8201(L) 6.2 Register 1 Basic Mode Status Address Name Description/Usage Default/Attribute 1:<15> 100Base-T4 100Base_T4: The RTL8201L supports the 100Base-T4 function. If the 0, RO chip is set to operate in this mode, this bit will return a ‘1’ when read. 1: Enable 100Base-T4 support 0: Suppress 100Base-T4 support 1:<14>...
  • Page 10: Register 2 Phy Identifier 1

    RTL8201(L) 1:<2> Link Status Link Status: The RTL8201L will return a ‘1’ on bit 2 when the link 0, RO state machine is in Link Pass, indicating that a valid link has been established. Otherwise, it will return ‘0’. When a link failure occurs after the link pass state has been entered, the Link Status bit will be latched at ‘0’...
  • Page 11: Register 4 Auto-Negotiation Advertisement

    RTL8201(L) 6.5. Register 4 Auto-negotiation Advertisement (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-negotiation. Address Name Description/Usage Default/Attribute 4:<15> Next Page: The RTL8201L does not implement the Next Page function, 0, RO so bit 15 will always return a ‘0’...
  • Page 12: Register 5 Auto-Negotiation Link Partner Ability

    RTL8201(L) 4:<6> 10FD 10Base-T-FD: This bit advertises the ability to the Link Partner that the 1, RW RTL8201L can operate in 10Base-T full duplex mode. Writing a ‘0’ to this bit will suppress the transmission of this ability to the Link Partner. Resetting the chip will restore the default value.
  • Page 13 RTL8201(L) 5:<8> TXFD 100Base-TX-FD: This bit indicates that the Link Partner can support 0, RO 100Base-TX full duplex mode. This bit is cleared any time Auto-negotiation is restarted or the RTL8201L is reset. 1: 100Base-TX full duplex is supported by link partner 0: 100Base-TX full duplex not supported by link partner 5:<7>...
  • Page 14: Register 6 Auto-Negotiation Expansion (Aner)

    RTL8201(L) 6.7 Register 6 Auto-negotiation Expansion (ANER) This register contains additional status for NWay auto-negotiation. Address Name Description/Usage Default/Attribute 6:<15:5> Reserved Reserved: Ignore the output of the RTL8201L when these bits are read. This bit is always set to 0. 6:<4>...
  • Page 15: Register 17 Loopback, Bypass, Receiver Error Mask (Lbremr)

    RTL8201(L) 6.9 Register 17 Loopback, Bypass, Receiver Error Mask (LBREMR) Address Name Description/Usage Default/Attribute 17:<15> RPTR Set to 1 to put the RTL8201(L) into repeater mode 0, RW 17:<14> BP_4B5B Assertion of this bit allows bypassing of the 4B/5B & 5B/4B encoder. 0, RW 17:<13>...
  • Page 16: Register 21 Phy 1_2

    RTL8201(L) 6.13 Register 21 PHY 1_2 Address Name Description/Usage Default/Attribute 21:<15:0> PHY1_2 PHY 1 register (functions as RTL8139C<78>) 6.13 Register 22 PHY 2 Address Name Description/Usage Default/Attribute 22<15:8> PHY2_76 PHY2 register for cable length test (functions as RTL8139C<76>) 22:<7:0> PHY2_80 PHY2 register for PLL select (functions as RTL8139C<80>) 6.14 Register 23 Twister_1 Address...
  • Page 17: Functional Description

    RTL8201(L) 7. Functional Description The RTL8201(L) Phyceiver is a physical layer device that integrates 10Base-T and 100Base-TX functions and some extra power manage features into a 48 pin single chip which is used in 10/100 Fast Ethernet applications. This device supports the following functions: MII interface with MDC/MDIO management interface to communicate with MAC IEEE 802.3u clause 28 Auto-Negotiation ability...
  • Page 18: Auto-Negotiation And Parallel Detection

    RTL8201(L) 7.2 Auto-negotiation and Parallel Detection The RTL8201(L) supports IEEE 802.3u clause 28 Auto-negotiation operation which can cooperate with other transceivers supporting auto-negotiation. By this mechanism, the RTL8201(L) can auto detect the link partner’s ability and determine the highest speed/duplex configuration and transmit/receive in this configuration. If the link partner does not support Auto-negotiation, then the RTL8201(L) will enable half duplex mode and enter parallel detection.
  • Page 19: Hardware Configuration And Auto-Negotiation

    RTL8201(L) 7.4 Hardware Configuration and Auto-negotiation This section describes methods to configure the RTL8201(L) and set the auto-negotiation mode. This list will show the various pins and their setting to provide the desired result. 1) Isolate pin: Set high to isolate the RTL8201(L) to MAC. This will also isolate the MDC/MDIO management interface. In this mode, power consumption is minimum.
  • Page 20: Led And Phy Address Configuration

    RTL8201(L) 7.5 LED and PHY Address Configuration In order to reduce the pin count on the RTL8201, the LED pins are duplexed with the PHY address pin. Because the PHYAD strap options share the LED output pins, the external combinations required for strapping and LED usage must be considered in order to avoid contention.
  • Page 21: Power Down, Link Down, Power Saving, And Isolation Modes

    RTL8201(L) 7.7 Power Down, Link Down, Power Saving, and Isolation Modes The RTL8201(L) supplies 4 kinds of Power Saving mode operation. This section will discuss all four, including how to implement each mode. The first three modes are configured through software, and the fourth through hardware. 1) Analog off: Setting bit 11 of register 17 to 1 will put the RTL8201(L) into analog off state.
  • Page 22: 10Base Tx/Rx

    RTL8201(L) 7.8.2 10Base Tx/Rx 1) 10Base Transmit Function: The 10Base transmit function is performed as follows: The transmit 4 bits nibbles(TXD[0:3]) clocked in 2.5MHz(TXC) is first feed to parallel to serial converter, then put the 10Mbps NRZ signal to Manchester coding.
  • Page 23: Electrical Characteristics

    RTL8201(L) 8. Electrical Characteristics 8.1 D.C. Characteristics 8.1.1. Absolute Maximum Ratings Symbol Conditions Minimum Typical Maximum Supply Voltage 3.0V 3.3V 3.6V Storage Temp. -55°C 125°C 8.1.2. Operating Conditions Symbol Conditions Minimum Typical Maximum Supply voltage 3.0V 3.3V 3.6V Operating Temperature 0°C 70°C 8.1.3.
  • Page 24: Characteristics

    RTL8201(L) 8.2 A.C. Characteristics 8.2.1 Transmission Without Collision Shown is an example transfer of a packet from MAC to PHY. 8.2.2 Reception Without Error Shown is an example of transfer of a packet from PHY to MAC 2002-01-18 Rev.1.04 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
  • Page 25: Mechanical Dimensions

    9° 0° 3.5° 9° θ1 CHECK DWG NO. SS048 - P1 0° 0° θ2 DATE Sept. 25.2000 12° TYP 12° TYP θ3 12° TYP 12° TYP REALTEK SEMI-CONDUCTOR CORP. 2002-01-18 Rev.1.04 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...
  • Page 26 RTL8201(L) Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2002-01-18 Rev.1.04 Tel: +49(0)234-9351135 · Fax: +49(0)234-9351137 E -MAIL: info@cornelius-consult.de http://www.cornelius-consult.de...

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