Watchdog Timer - Technologic Systems TS-5700 User Manual

TS-5700 User's Manual

13 Watchdog Timer

The AMD Elan520 contains a 32-bit watchdog timer (WDT) unit
that can be used to prevent a system "hanging" due to a software
failure. The WDT can be programmed to cause an interrupt or a
full system reset when the WDT times out allowing a guaranteed
recovery time from a software error. To prevent a WDT timeout,
the application must periodically "feed" the WDT by writing a
"clear-count key sequence" to the Watchdog Timer Control
(WDTMRCTL) register.
The WDT must be initialized with the timeout period desired. This
may be as short as 0.5 mS or may be as high as 32 seconds.
After the WDT has been enabled, the 32-bit watchdog counter
starts counting from zero. The application software can reset this
counter at any time by writing a "clear-count key sequence" to the
WDTMRCTL. If this counter reaches the timeout period, then an interrupt is generated, or a system reset occurs.
If programmed to cause an interrupt, the WDT must be fed within the next timeout period or
else a system reset occurs as an additional failsafe feature.
In order to load the WDTMRCTL register, a specific sequence of three word writes is
required. A 3333h, followed by CCCCh, followed by the value to be loaded into the
WDTMRCTL register must be written to the WDTMRCTL register.
In order to clear the WDT counter (feeding the watchdog), a "clear-count key sequence"
must be written to the WDTMRCTL register. This is a specific two word write sequence
with a write of AAAAh, followed by a write of 5555h. (Writing this "clear-count key
sequence" has no effect on the contents of the WDTMRCTL register)
Typically a system reset at timeout is the preferred method for using the WDT, if you wish
to have an interrupt occur before the system reset occurs (bit 14 = 0 in the WDTMRCTL
Register), additional programming is required to "attach" a specific IRQ to the WDT. An
interrupt service routine must also be written to handle this IRQ. Please download the
Elan SC520 user's manual
When using the Linux OS, we provide a driver to initialize
and "feed" the WDT. We also provide a Linux sample
application program with full source.
Technologic Systems
or contact Technologic Systems.
22
Table 13a WDTMRCTL Register
Bit Position
Bit 15 1 = Enable WDT
Bit 14 1 = Generate Reset at Timeout
0 = Generate Interrupt at Timeout
Bit 13 Must always be 0
Bit 12 1 = WDT Interrupt has occurred
(Interrupt reoutine must clear this bit)
Bits 8-11 Must always be 0
Bits 0-7 Timeout Value (See Table 4)
AMD
Table 13c WatchDog Timer Memory Map
Register
WatchDog Control (WDTMRCTL)
WDT Counter Bits 0-15 (Read Only)
WDT Counter Bits 16-31 (Read Only) DFCB4h
WDT Interrupt Mapping
http://embeddedARM.com/
Function
Table 13b WatchDog
Timer Timeout Values
Bits 0-7 Timeout Value
01h 0.5 milliseconds
02h 0.5 seconds
04h 1 second
08h 2 seconds
10h 4 seconds
20h 8 seconds
40h 16 seconds
80h 32 seconds
Memory Address
DFCB0h
DFCB2h
DFD42h
5/2009