Spi Bus; Hardware - Technologic Systems TS-5700 User Manual

TS-5700 User's Manual

11 SPI Bus

11.1 Hardware

The SPI bus is a three-wire interface that allows high-speed serial
communications using low-pin count peripherals. The SPI bus is a
byte-oriented bus, so 16-bit transfers need to use two back-to-back byte
transfer cycles.
The SPI bus is available on a 10-pin header. Tables 11.1a and 11.1b
document the Header pin-outs. Additional off-board chips may be added to
the SPI bus.
Warning: The TS-5700 has an eeprom using the SPI bus running at 3.3V and
is not 5V tolerant. This means that any devices that are added to the SPI
bus must not drive the SPI data input (pin 5) any higher than 3.3V.
Alternatively, a 5V device can be added if a series resistor (470 ohm) is
added to the SPI Data input line to limit the current.
There are 5 registers that control the
Elan520 SPI bus:
Control Register Address = DFCD0h
TX data Register Address = DFCD1h
RX data Register Address = DFCD4h
Command Register Address = DFCD2h
Status Register Address = DFCD3h
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Table 11.1a SPI Bus
Header
Pin Description
1 SPI Data (out)
2 5V Power
3 SPI CLK (out)
4 GND
5 SPI Data (in)
6 GND
7 PIO4 (Chip Select)
8 PIO5 (Chip Select)
9 PIO6 (Chip Select)
10 PIO7 (Chip Select)
Table 11.1b
SPI Bus
Header
Pinout
2 4 6 8 10
1 3 5 7 9
5/2009