Automatic Rs-485 Tx Enable; Adding Serial Ports; Com3 And Com4 Interrupt Configuration Register - Technologic Systems TS-5700 User Manual

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TS-5700 User's Manual

5.4 Automatic RS-485 TX Enable

TS-5700 boards support fully automatic TX enable control. This simplifies the design of half-duplex systems
since turning off the transmitter via the RTS signal is typically difficult to implement. The COM1 UART transmit
holding register and the transmit shift register both must be polled until empty before deasserting RTS when
using the RTS mode. The design gets more difficult when using the TX FIFO or when using a multi-tasking OS
such as Linux.
In Automatic mode, Timer2 and a Xilinx PLD keep track of the bits shifting out the COM1 UART. This circuit
automatically turns on/off the RS-485 transceiver at the correct times. This only requires the TIMER2 to be
initialized once based on baud rate and data format, and bit 7 at I/O location 75 must be set. The utility called
AUTO485.exe is included in the /util directory.

5.5 Adding Serial Ports

If your project requires more than four serial ports, additional ports may be added via the PC/104 expansion bus.
Technologic Systems offers three different peripheral boards (TS-SER1, TS-SER2, and TS-SER4) that add 1,2,
or 4 extra COM ports respectively. Typically these would be configured as COM5 or be assigned other higher
COM I/O locations. Because DOS only directly supports four serial ports, any additional ports beyond four will
require software drivers if using DOS.
The TS-5700 PC/104 bus has IRQ 7, 9, 12 or 15 available for additional serial ports.
Note: IRQ7 is used by many PCMCIA cards.
Typically each serial port has a dedicated interrupt, but the TS-SER4 allows all four extra serial ports to share a
single interrupt. This is very helpful in systems with a large number of serial ports since there are a limited
number of IRQ lines available.

5.6 COM3 and COM4 Interrupt Configuration Register

To configure COM3 and COM4 interrupts write to the Interrupt Configuration bits in I/O space at address 79h.
The reset condition has no interrupt configured for COM3 or COM4. See the table below for details.
Table 5.6 COM3 and COM4 Interrupt Configuration Register
Bit1
Bit0
COM3-COM4 Interrupt Configuration
0
0
No IRQ driven by COM3 or COM4 (default at reset)
0
1
COM3 drives IRQ5, COM4 drives IRQ6
1
0
COM3 and COM4 share IRQ5
1
1
COM3 and COM4 share IRQ6
Technologic Systems
at I/O 79h
10
http://embeddedARM.com/
5/2009

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