Block Diagram Analysis; Input Signal Conditioners - Fluke 8020A Instruction Manual

3-6. Timing for the overall operation of the a/d
converter is derived from an external quartz crystal
whose frequency is selected to be a multiple of the local
line frequency. This allows the conditioned dc input
data to be intergrated over a single line cycle, thus,
optimizing both common mode apd normal mode
rejection.
3-7. Digitized measurement data is presented to the
display as four decoded digits (seven segments) plus
polarity. Decimal point position on the display is
determined by the range switch settings.
3-8.

BLOCK DIAGRAM ANALYSIS

3-10. The entire analog-to-digital conversion process
is accomplished by a single custom a / d converter and
Display Driver lC, U8. The 1C employs the dual slope
method of a / d conversion, and requires a series of
external components to establish the basic timing and
reference levels required for operation. These include a
3.2 MHz crystal, an integrating capacitor, an autozero
capacitor, and a flying capacitor (for applying a reference
level of either polarity). Since the power consumed for
display operation is very low, the a / d converter IC also
contains the display latches, decoders and drivers.
3-11. The digital control portion of the a / d con-
version process is an internal function of U8, and is
keyed to the external crystal frequency. As a result, the
conversion process is continuously repeated, and the
display is updated at the end of the every conversion
cycle.
3-12. A simplified circuit diagram of the analog
portion of the a / d converter is shown in Figure 3-2.
Each of the switches shown represent analog gates
which are operated by the digital section of the a/d
converter. Basic timing for switch operation and,
therefore, a complete measurement cycle is also included
in the figure.
3-13. Any given measurement cycle performed by the
periods, autozero (AZ), integrate (INTEG), and read.
Both autozero and integrate are fixed time periods whose
lengths are multiples of a 6Q kHz clock. A counter
determines the length of both time periods by providing
an overflow at the end of every 10,000 clock pulses. The
read period is a variable time which is proportional to the
unknown input voltage. The value of the voltage is
determined by counting the number of clock pulses that
occur during the read period.
3-14.
During autozero a ground reference is applied
as an input to the a/d converter. Under ideal conditions
the output of the comparator would also go to zero.
However, input-offset-voltage errors accumulate in the
amplifier loop, and appear at the comparator output as
an error voltage. This error is impressed across the AZ
capacitor where it is stored for the remainder of the
measurement cycle. The stored level is used to provide
offset voltage correction during the integrate and read
periods.
3-15. The integrate period begins at the end of the
opens and the INTEG switch closes. This applies the
unknown input voltage to the input of the a/d converter.
The voltage is buffered and passed on to the integrator
to determine the charge rate (slope) on the INTEG
capacitor. At the end of the fixed integrate period the
capacitor is charged to a level proportional to the
unknown input voltage. This voltage is translated to a
digital indication by discharging the capacitor at a fixed
rate during the read period, and counting the number of
clock pulses that occur before it returns to the original
3-16. As the read period begins, the INTEG switch
opens and the read switch closes. This applies a known
reference voltage to the input of the a / d converter. The
polarity of this voltage is automatically selected to be
opposite that of the unknown input voltage, thus,causing
the INTEG capacitor to discharge at a fixed rate (slope).
When the charge is equal to the initial starting point
(autozero level), the read period is ended. Since the
discharge slope is fixed during the read period, the time
required for discharge is proportional to the unknown
input voltage.
3-17. The
measurement cycle begins at the end of the read period.
At the same time the counter is released for operation by
transferring its contents (previous measurement value)
to a series of latches. This stored data is then decoded
and buffered before being used for driving the liquid
crystal display.
3-18. Input Signai Conditioners
3-19. The a / d converter requires two externally
supplied input voltages to complete a measurement cycle.