Maxim DS80C400 User Manual

Network microcontroller

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GENERAL DESCRIPTION
The DS80C400 network microcontroller offers the highest
integration available in an 8051 device. Peripherals include
a 10/100 Ethernet MAC, three serial ports, a CAN 2.0B
®
controller, 1-Wire
Master, and 64 I/O pins.
To enable access to the network, a full application-
accessible TCP IPv4/6 network stack and OS are provided
in ROM. The network stack supports up to 32 simultaneous
TCP connections and can transfer up to 5Mbps through the
Ethernet MAC. Its maximum system-clock frequency of
75MHz results in a minimum instruction cycle time of 54ns.
Access to large program or data memory areas is
simplified with a 24-bit addressing scheme that supports up
to 16MB of contiguous memory.
To accelerate data transfers between the microcontroller
and memory, the DS80C400 provides four data pointers,
each of which can be configured to automatically increment
or decrement upon execution of certain data pointer-related
instructions. The DS80C400's hardware math accelerator
further increases the speed of 32-bit and 16-bit multiply
and divide operations as well as high-speed shift,
normalization, and accumulate functions.
The High-Speed Microcontroller User's Guide and the High-Speed
Microcontroller User's Guide: DS80C400 Supplement should be
used in conjunction with this data sheet. Download both at:
www.maxim-ic.com/microcontrollers.
APPLICATIONS
Industrial Control/Automation
Environmental Monitoring
Network Sensors
Vending
Home/Office Automation
ORDERING INFORMATION
PART
TEMP RANGE
DS80C400-FNY
-40°C to +85°C
1-Wire is a registered trademark of Dallas Semiconductor.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
Data Converters (Serial-to-
Ethernet, CAN-to-
Ethernet)
Remote Data Collection
Equipment
Transaction/Payment
Terminals
MAX CLOCK
PIN-
SPEED
PACKAGE
75MHz
100 LQFP
1 of 96
Network Microcontroller
FEATURES
§
High-Performance Architecture
Single 8051 Instruction Cycle in 54ns
DC to 75MHz Clock Rate
Flat 16MB Address Space
Four Data Pointers with Auto-Increment/
Decrement and Select-Accelerate Data Movement
16/32-Bit Math Accelerator
§
Multitiered Networking and I/O
10/100 Ethernet Media Access Controller (MAC)
CAN 2.0B Controller
1-Wire Net Controller
Three Full-Duplex Hardware Serial Ports
Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O
Pins)
§
Robust ROM Firmware
Supports Network Boot Over Ethernet Using DHCP
and TFTP
Full, Application-Accessible TCP/IP Network Stack
Supports IPv4 and IPv6
Implements UDP, TCP, DHCP, ICMP, and IGMP
Preemptive, Priority-Based Task Scheduler
MAC Address can Optionally be Acquired from IEEE-
Registered DS2502-E48
§
10/100 Ethernet Mac
Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC
(10Mbps) Interfaces Allow Selection of PHY
Low-Power Operation
Ultra-Low-Power Sleep Mode with Magic Packet
and Wake-Up Frame Detection
8kB On-Chip Tx/Rx Packet Data Memory with Buffer
Control Unit Reduces Load on CPU
Half- or Full-Duplex Operation with Flow Control
Multicast/Broadcast Address Filtering with VLAN
Support
§
Full-Function CAN 2.0B Controller
15 Message Centers
Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks
Media Byte Filtering to Support DeviceNet
Higher Layer CAN Protocols
Auto-Baud Mode and SIESTA Low-Power Mode
§
Integrated Primary System Logic
16 Total Interrupt Sources with Six External
Four 16-Bit Timer/Counters
2x/4x Clock Multiplier Reduces Electromagnetic
Interference (EMI)
Programmable Watchdog Timer
Oscillator-Fail Detection
Programmable IrDA Clock
Features continued on page 32.
Pin Configuration appears at end of data sheet.
DS80C400
, SDS, and
REV: 102103

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Summary of Contents for Maxim DS80C400

  • Page 1 Pin Configuration appears at end of data sheet. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 96...
  • Page 2: Absolute Maximum Ratings

    DS80C400 Network Microcontroller ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Input Pin Relative to Ground -0.5V to +5.5V Voltage Range on Any Output Pin Relative to Ground -0.5V to (V + 0.5)V Voltage Range on V Relative to Ground -0.5V to +3.6V...
  • Page 3 DS80C400 Network Microcontroller most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset. Note 3: While the specifications for V and V overlap, the design of the hardware makes it such that this is not possible.
  • Page 4: External Clock Drive

    DS80C400 Network Microcontroller EXTERNAL CLOCK OSCILLATOR (XTAL1) CHARACTERISTICS PARAMETER SYMBOL UNITS See External Clock Clock Oscillator Period Oscillator Frequency Clock Symmetry at 0.5 x V 0.45 t 0.55 t Clock Rise Time Clock Fall Time EXTERNAL CLOCK DRIVE XTAL1 SYSTEM CLOCK TIME PERIODS (t...
  • Page 5 DS80C400 Network Microcontroller STRETCH VALUES PARAMETER SYMBOL UNITS (MD2:0) CLCL Data Float After RD (P3.7 or £ 3 1£ C RHDZ CLCL PSEN) High 4 £ C £ 7 CLCL - 19 CLCL CLCH ALE Low to Valid Data In...
  • Page 6 DS80C400 Network Microcontroller 6 of 96...
  • Page 7 DS80C400 Network Microcontroller 7 of 96...
  • Page 8 DS80C400 Network Microcontroller MULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ PORT 4 – CE0 - PORT 6 – A16 -A21 A16 -A21 PORT 4/6 ADDRESS A16 -A21 A16 -A21 MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 - PORT 6 –...
  • Page 9 DS80C400 Network Microcontroller MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 - PORT 6 –...
  • Page 10 DS80C400 Network Microcontroller MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 - PORT 6 –...
  • Page 11 DS80C400 Network Microcontroller MULTIPLEXED, 9-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 - PORT 6 –...
  • Page 12 DS80C400 Network Microcontroller MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 - PORT 6 – PORT 4/6 A16 -A21 A16 -A21 A16 -A21 A16 -A21 ADDRESS 12 of 96...
  • Page 13 DS80C400 Network Microcontroller ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1) = 3.0V to 3.6V, V = 1.8V ±10%, T = -40°C to +85°C.) 75MHz VARIABLE CLOCK PARAMETER SYMBOL UNITS External Crystal Frequency 1 / t Clock Mutliplier 2X Mode 37.5 Clock Multiplier 4X Mode 18.75...
  • Page 14 DS80C400 Network Microcontroller MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1) = 3.0V to 3.6V, V = 1.8V +±10%, T = -40°C to +85°C.) STRETCH PARAMETER SYMBOL UNITS VALUES (MD2:0) CLCL Input Instruction Float After PSEN £ 3 1£ C PXIZ CLCL 4 £...
  • Page 15 DS80C400 Network Microcontroller 15 of 96...
  • Page 16 DS80C400 Network Microcontroller 16 of 96...
  • Page 17 DS80C400 Network Microcontroller NONMULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 - PORT 6 –...
  • Page 18 DS80C400 Network Microcontroller NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 –...
  • Page 19 DS80C400 Network Microcontroller NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 - PORT 6 –...
  • Page 20 DS80C400 Network Microcontroller NONMULTIPLEXED, 9-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 PORT 7 NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 –...
  • Page 21 DS80C400 Network Microcontroller NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 - PORT 6 – PORT 4/6 ADDRESS A16 -A21 A16 -A21 A16 -A21 A16 -A21 PORT 7 OW PIN TIMING CHARACTERISTICS (Note 1) = 3.0V to 3.6V, V = 1.8V ±10%, T...
  • Page 22 DS80C400 Network Microcontroller OW PIN TIMING 22 of 96...
  • Page 23 DS80C400 Network Microcontroller PIN TIMING CHARACTERISTICS (Note 1) OWSTP = 3.0V to 3.6V, V = 1.8V ±10%, T = -40°C to +85°C.) STANDARD OVERDRIVE PARAMETER SYMBOL UNITS Active Time for Presence Detect Active Time for Presence Detect Recovery Active Time for Write 1 Recovery (Notes 2, 3) 51.2...
  • Page 24 DS80C400 Network Microcontroller ETHERNET MII INTERFACE TIMING CHARACTERISTICS (Note 1) = 3.0V to 3.6V, V = 1.8V ±10%, T = -40°C to +85°C.) 100Mbps 10Mbps PARAMETER SYMBOL UNITS TXClk Duty Cycle TXD, TX_EN Data Setup to TXClk TXD, TX_EN Data Hold from TXClk...
  • Page 25 DS80C400 Network Microcontroller SERIAL PORT MODE 0 TIMING CHARACTERISTICS (Note 1) = 3.0V to 3.6V, V = 1.8V ±10%, T = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS UNITS SM2 = 0:12 clocks per cycle 12 t CLCL Serial Port Clock Cycle Time...
  • Page 26 DS80C400 Network Microcontroller SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH-SPEED OPERATION, TXD CLK = SYSCLK/4 (SM2 = 1) TRADITIONAL 8051 OPERATION, TXD CLOCK = XTAL/12 (SM2 = 0) 26 of 96...
  • Page 27: Power Cycle Timing

    DS80C400 Network Microcontroller POWER CYCLE TIMING CHARACTERISTICS PARAMETER SYMBOL UNITS Crystal Startup Time (Note 1) Power-On Reset Delay (Note 2) 65,536 CLCK Note 1: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox Electronics.
  • Page 28: Block Diagram

    DS80C400 Network Microcontroller BLOCK DIAGRAM P0.0–P0.7 P1.0–P1.7 PORT 1 PORT 0 SERIAL 1-WIRE PORT 1 CONTROLLER PORT LATCH TIMER 2 PORT LATCH PORT 5 P5.0–P5.7 28 of 96...
  • Page 29: Pin Description

    RST1 RST3 DS80C400 to an external PHY, do not connect the RSTOL to the reset of the PHY. Doing so may disable the Ethernet transmit. XTAL1, XTAL2. Crystal oscillator pins support fundamental mode, parallel resonant, AT cut crystals. XTAL1 is XTAL2 the input if an external clock source is used in place of a crystal.
  • Page 30 DS80C400 Network Microcontroller NAME FUNCTION P2.2 A10 Program/Data Memory Address 10 P2.3 A11 Program/Data Memory Address 11 P2.4 A12 Program/Data Memory Address 12 P2.5 A13 Program/Data Memory Address 13 P2.6 A14 Program/Data Memory Address 14 P2.7 A15 Program/Data Memory Address 15 Port 3, I/O.
  • Page 31 DS80C400 Network Microcontroller NAME FUNCTION CE5 Program Memory Chip Enable 5 P6.1 P6.5 CE6 Program Memory Chip Enable 6 P6.2 CE7 Program Memory Chip Enable 7 P6.3 P6.6 P6.4 A20 Program/Data Memory Address 20 P6.5 A21 Program/Data Memory Address 21 P6.6...
  • Page 32: Detailed Description

    32-bit and 16-bit multiply and divide operations as well as high-speed shift, normalization, and accumulate functions. With extensive networking and I/O capabilities, the DS80C400 is equipped to serve as a central controller in a multitiered network. The 10/100 Ethernet media access controller (MAC) enables the DS80C400 to access and communicate over the Internet.
  • Page 33 The microcontroller can be configured to automatically switch back from PMM to the faster mode in response to external interrupts or serial port activity. The DS80C400 provides the ability to place the CPU into an idle state or an ultra-low-power stop-mode state. As protection against brownout and power-fail conditions, the microcontroller is capable of issuing an early warning power-fail interrupt and can generate a power- fail reset.
  • Page 34: Performance Overview

    8051 instruction set. When writing software to use a new feature, an equate statement defines the SFR to the assembler or compiler. This is the only change needed to access the new function. The DS80C400 duplicates the SFRs contained in the standard 80C32.
  • Page 35 DS80C400 Network Microcontroller Table 1. SFR Addresses and Bit Locations REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS P4.7/A19 P4.6/A18 P4.5/A17 P4.4/A16 P4.3/CE3 P4.2/CE2 P4.1/CE1 P4.0/CE0 DPL1 DPH1 SEL1 —...
  • Page 36 DS80C400 Network Microcontroller REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS C0M9C MSRDY INTRQ EXTRQ MTRQ ROW/TIH DTUP C0M10C MSRDY INTRQ EXTRQ MTRQ ROW/TIH DTUP — SADEN0 SADEN1 C0M11C MSRDY...
  • Page 37 DS80C400 Network Microcontroller REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS DPH2 DPL3 DPH3 DPS1 — — — — — — STATUS1 — — — — V1PF V3PF SPTA2 SPRA2...
  • Page 38 DS80C400 Network Microcontroller Table 2. SFR Reset Values REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS DPL1 DPH1 PCON Special TCON TMOD CKCON EXIF Special Special Special P4CNT DPX1 C0RMS0...
  • Page 39 DS80C400 Network Microcontroller REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS STATUS MCON T2CON T2MOD RCAP2L RCAP2H MCNT0 MCNT1 MCON1 MCON2 WDCON Special Special Special SADDR2 BPA1 BPA2 BPA3 OCAD...
  • Page 40: Memory Architecture

    Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address bus/8-bit data bus through eight available chip enables. Up to 4MB of external data memory can be accessed over the same address/data buses through peripheral-enable signals. The DS80C400 also permits a 16MB merged program/data memory map.
  • Page 41: Addressing Modes

    SP;81h External Program Memory Addressing Since the DS80C400 is not bound to the 8051’s traditional 16-bit address mode, on-chip hardware enhancements were made to accommodate the larger memory interfaces associated with 24-bit addressing. The DS80C400 provides SFR bits to configure certain port pins as upper address lines and chip enables. The Port 4 control register (P4CNT;...
  • Page 42 MSB presented on Port 2 and the address LSB and data multiplexed on Port 0. The multiplexed mode requires an external latch to demultiplex the address LSB and data. The DS80C400 provides an external pin ( MUX ) that, when pulled high during a power-on reset, demultiplexes the address LSB and data.
  • Page 43 When combined program/data memory access is enabled, there is the potential to inadvertently modify code that a user meant to leave fixed. For this reason, the DS80C400 provides the ability to write protect the first 0–16kB of memory accessible through each of the chip enables CE3 , CE2 , CE1 , and CE0 . The write-protection feature for each chip enable is invoked by setting the appropriate WPE3–0 (MCON2.3-0) bit.
  • Page 44 SFR address locations not used in the original 8051. To access the extended 24-bit address range supported by the DS80C400, a third, high-order byte (DPXn) has been added to each pointer so that each data pointer is now composed of the SFR combination DPXn+DPHn+DPLn.
  • Page 45 SEL are not implemented so that the INC DPS instruction can still be used to quickly toggle between DPTR0 and DPTR1 or between DPTR2 and DPTR3. Unlike the standard 8051, the DS80C400 has the ability to decrement as well as increment the data pointers without additional instructions. Each data pointer (DPTR0, DPTR1, DPTR2, DPTR3) has an associated control bit (ID0, ID1, ID2, ID3) that determines whether the INC DPTR operation results in an increment or decrement of the pointer.
  • Page 46 MOVX @DPTR, A Stretch Memory Cycles The DS80C400 allows user-application software to select the number of machine cycles it takes to execute a MOVX instruction, allowing access to both fast and slow off-chip data memory and/or peripherals without glue logic. High-speed systems often include memory-mapped peripherals such as LCDs or UARTs with slow access times, so it may not be necessary or desirable to access external devices at full speed.
  • Page 47 Internal MOVX SRAM The DS80C400 contains 9kB of SRAM that is physically divided into a 1kB block and an 8kB block. The 1kB block can be used to support the extended stack-pointer function or can be used as general-purpose MOVX data memory.
  • Page 48 DS80C400 Network Microcontroller facilitates the conversion of 4-Byte unsigned binary integers into floating point format. Table 11 shows the operations supported by the math accelerator and their time of execution. Table 11. Arithmetic Accelerator Execution Times OPERATION RESULT EXECUTION TIME...
  • Page 49: Ethernet Controller

    RECEIVE, AND ADDRESS CHECK FLOW CONTROL) BLOCK DS80C400 ON-CHIP ETHERNET CONTROLLER NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE RSTOL TO THE RESET OF THE PHY. DOING SO MAY DISABLE THE ETHERNET TRANSMIT. 49 of 96...
  • Page 50 DS80C400 Network Microcontroller Buffer Control Unit The buffer control unit (BCU) serves as the central controller of all DS80C400 Ethernet activity. The BCU regulates CPU read/write activity to the Ethernet controller blocks through a series of SFRs: BCU control (BCUC; E7h), BCU data (BCUD;...
  • Page 51 DS80C400 Network Microcontroller aborted. The BCU incorporates a 31 x 8 first-in-first-out receive packet register (receive FIFO) so that the CPU can access information for the next receive packet in queue. Upon reception of each valid packet into receive buffer memory, the BCU writes a receive status word into the first word of the receive packet starting page, updates the receive FIFO, and notifies the CPU by setting an interrupt flag.
  • Page 52 DS80C400 Network Microcontroller Each CSR register is documented as follows: CSR Register: MAC Control Register Address: Bit Names: — — — — OM[1:0] — DRTY — ASTP BLOMT[1:0] — — — Reset State: RA, Receive All. This bit overrides the flush-filter failed-packet function if that function has been enabled (EBS.7 = 1).
  • Page 53 DS80C400 Network Microcontroller IF, Inverse Filtering 0 = inverse filtering disabled (default) 1 = inverse filtering by the address check block enabled PB, Pass Bad Frames 0 = packet filter bit in the receive status word is set (= 1) only when error-free frames received (default) 1 = packet filter bit in the receive status word is set (= 1) for frames that pass the destination address filter even when they contain errors.
  • Page 54 DS80C400 Network Microcontroller CSR Register: MAC Address High Register Address: Bit Names: — — — — — — — — — — — — — — — — PADR [47:40] PADR [39:32] Reset State: PADR [47:32]m MAC Physical Address [47:32]. These two bytes represent the 16 most significant bits of the MAC physical address.
  • Page 55 DS80C400 Network Microcontroller CSR Register: Multicast Address High Register Address: Bit Names: HT[63] HT[62] HT[61] HT[60] HT[59] HT[58] HT[57] HT[56] HT[55] HT[54] HT[53] HT[52] HT[51] HT[50] HT[49] HT[48] HT[47] HT[46] HT[45] HT[44] HT[43] HT[42] HT[41] HT[40] HT[39] HT[38] HT[37] HT[36]...
  • Page 56 DS80C400 Network Microcontroller CSR Register: MII Address Register Address: Bit Names: — — — — — — — — — — — — — — — — PHYA [4:0] PHYR [4:2] PHYR [1:0] — — — — BUSY W/ R Reset State: PHYA[4:0], PHY Address [4:0].
  • Page 57 DS80C400 Network Microcontroller CSR Register: Flow Control Register Address: Bit Names: PAUSE [15:8] PAUSE [7:0] — — — — — — — — — — — — — BUSY Reset State: PAUSE[15:0], Pause Time [15:0]. These bits are only valid in full-duplex mode. These 16 bits contain the value that is passed in the pause time field when a pause-control frame is generated.
  • Page 58 DS80C400 Network Microcontroller CSR Register: VLAN1 Tag Register Address: Bit Names: — — — — — — — — — — — — — — — — VLAN1 [15:8] VLAN1 [7:0] Reset State: VLAN1 [15:0], VLAN1 Tag Identifier [15:0]. These 16 bits contain the VLAN1 tag that is compared against the 13th and 14th bytes of the incoming frame to determine whether it is a VLAN1 frame.
  • Page 59 DS80C400 Network Microcontroller CSR Register: Wake-Up Frame Filter Register Address: Bit Names: WUFD [31:24] WUFD [23:16] WUFD [15:8] WUFD [7:0] Reset State: WUFD [31:0], Wake-Up Frame Filter Data [31:0]. These 32 bits are used to access the four available network wake-up frame filters.
  • Page 60 MDIO SERIAL INTERFACE BUS TO PHY) NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE RSTOL TO THE RESET OF THE PHY. DOING SO MAY DISABLE THE ETHERNET TRANSMIT. MII Management Block The MII management block allows the host to write control data to and read status from any of 32 registers in any of 32 PHY controllers.
  • Page 61 DS80C400 Network Microcontroller MII I/O Block The MII I/O block supports all of the transmit and receive data transactions between the DS80C400 MAC and the external PHY device as well as monitoring network status signals provided by the PHY. The transmit interface is composed of TXCLK, TX_EN, and TXD[3:0]. The TXCLK input is the transmit clock provided by the PHY.
  • Page 62 DS80C400 Network Microcontroller Address Check Block The address check block of the Ethernet controller monitors the destination address of all incoming packets and determines whether the address passes or fails the filter criteria configured by CPU. The outcome of this address filter test, along with bits signaling whether the frame is a broadcast or multicast frame, is reported by the BCU in a packet’s receive status word.
  • Page 63: Vlan Support

    1: Multicast Address High VLAN Support The DS80C400 offers VLAN support through recognition of frames that are tagged as such. Each VLAN tag provides tag control information (TCI) containing a tag protocol ID (TPID) and VLAN ID. The incoming TPID occupy the 13th and 14th byte positions, those that would normally contain either the length or type field for the frame.
  • Page 64 DS80C400 Network Microcontroller Transmit/Receive Packet Buffer Memory (8kB) The DS80C400 Ethernet controller uses 8kB of internal SRAM as transmit/receive packet buffer memory. This SRAM is read/write accessible as data memory by the CPU using the MOVX instruction. The BCU also has access to this SRAM, and automatically writes/reads packet buffer memory whenever it needs to store or retrieve Ethernet packet information.
  • Page 65 DS80C400 Network Microcontroller Transmit/Receive Status Words For each attempt made by the MAC to receive or transmit packet data, the BCU writes a 32-bit transmit or receive status word back to the first word of the starting page for the packet. This word provides status information needed by the CPU to determine when and what action should be taken.
  • Page 66 DS80C400 Network Microcontroller NOCRS, No Carrier. This bit is only valid in half-duplex mode. 0 = transmit frame was not aborted due to lack of carrier 1 = transmit frame aborted due to lack of carrier (CRS = 0 when transmit frame initiated)
  • Page 67 DS80C400 Network Microcontroller VLAN2, Two_Level VLAN Frame 0 = receive frame did not contain a VLAN tag that matched the VLAN2 register 1 = receive frame 13th and 14th bytes matched the two-level VLAN tag register (VLAN2) VLAN1, One_Level VLAN Frame...
  • Page 68: Ethernet Interrupts

    BCU reports the status of either a transmit or receive packet. Power Management Block The DS80C400 Ethernet controller contains a power management block that allows it to be put into a sleep mode by the CPU, thus conserving power when not actively handling Ethernet traffic.
  • Page 69 Once serial communication has been established at a supported baud rate, signified by correct reception of the DS80C400 loader banner and prompt, the user can issue commands. The serial loader commands are described later in the data sheet. If the serial loader pin is pulled to a logic 0, the ROM reads the state of port pin P5.3.
  • Page 70 DS80C400 Network Microcontroller Figure 12. ROM Code Boot Sequence POWER-ON RESET (BROM = 0) RESET STATE EA PIN? BROM BIT? ROM INIT SERIAL AUTO-BAUD SERIAL LOADER LOADER (P1.7) SUCCESS? PIN? ‘N’ ‘E’ NETBOOT NETBOOT (P5.3) PIN? FIND USER CODE RUN USER CODE...
  • Page 71: Internal Memory

    TINI400 ROM Initialization Code The TINI400 firmware automatically executes Initialization Code (ROM_Init) to generate the memory map as shown in Figure 13 and configure the DS80C400 hardware as follows: Enables 24-bit contiguous address mode (ACON.1:0 = 11b) Logically relocates ROM to addresses FF0000h–FF7FFFh (ACON.5 =1)
  • Page 72 The calculated reload value and clock frequency can be used in the equation to solve for the baud rate configurable by the DS80C400. It is advised that the baud rate mismatch be no greater than ±2.5% to maintain reliable communication.
  • Page 73 “next server IP” field. Because some DHCP servers do not allow configuration of the “next server IP” field, the DS80C400 recognizes the site-specific option 150 (also used on Cisco IP phones to get TFTP server IP addresses). When option 150 is present in the acknowledge packet, it will take precedence over the “next server IP”...
  • Page 74 DS80C400 Network Microcontroller Now armed with an IP address and TFTP server IP address, the DS80C400 tries to find code to be loaded into external program memory. The TINI400 ROM first requests to read the file from the TFTP server coinciding with its unique physical MAC address (e.g., 006035AB9811).
  • Page 75 ROM export table. Brief descriptions of the functionality provided by the TCP/IP stack, socket layer, and task manager are included after the table, while the full details for these and other exported ROM functions are covered in the High-Speed Microcontroller User’s Guide: DS80C400 Supplement.
  • Page 76 DS80C400 Network Microcontroller Table 18. ROM Export Table INDEX FUNCTION DESCRIPTION/GROUP Num_Fn,0,0 Number of functions following in the table crc16 Utility functions mem_clear mem_copy mem_compare add_dptr0 add_dptr1 sub_dptr0 sub_dptr1 getpseudorandom rom_kernelmalloc Memory manager rom_kernelfree rom_malloc rom_malloc_dirty rom_free rom_deref rom_getfreeram socket...
  • Page 77 DS80C400 Network Microcontroller INDEX FUNCTION DESCRIPTION/GROUP task_kill task_suspend task_sleep task_signal rom_task_switch_in rom_task_switch_out EnterCritSection Enter/Leave critical section LeaveCritSection rom_init Initialization functions rom_copyivt rom_redirect_init mm_init km_init ow_init network_init eth_init init_sockets tick_init WOS_Tick Timer interrupt handler BLOB Start address of the memory area ignored by NetBoot...
  • Page 78 Table 19 lists the socket functions implemented and accessible in the ROM firmware. The full details of each socket function are contained in the High-Speed Microcontroller User’s Guide: DS80C400 Supplement . Figure 19 illustrates the typical sequences for using TCP/UDP client/server sockets. The IPv4 implementation supports multicasting, ICMP echo request (“ping”), DHCP client, and TFTP client.
  • Page 79: Task Scheduler

    DS80C400 Supplement provides greater detail about the task scheduler and its functionality. Controller Area Network (CAN) Module The DS80C400 incorporates one CAN controller that is fully compliant with the CAN 2.0B specification. CAN is a highly robust, high-performance communication protocol for serial communications. Popular in a wide range of applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows for the construction of sophisticated networks with a minimum of external hardware.
  • Page 80 Modification of the CAN registers located in MOVX memory is protected through the SWINT bit. Consult the description of this bit in the High-Speed Microcontroller User’s Guide: DS80C400 Supplement for more information. The CAN module contains a block of control/status/mask registers, 14 functionally identical message centers, plus a 15th message center that is receive-only and incorporates a buffered FIFO.
  • Page 81 DS80C400 Network Microcontroller CAN Interrupts The DS80C400 provides one interrupt source for the CAN controller. The CAN interrupt source can be triggered by a receive/transmit acknowledgment from one of the 15 message centers or an error condition. Each message center has individual ETI (transmit) and ERI (receive) interrupt enable bits and INTRQ flag bits that are found in the corresponding message control (C0MxC) SFR.
  • Page 82 DS80C400 Network Microcontroller Table 21. Arbitration/Masking Feature Summary ARBITRATION CONTROL BITS TEST NAME MASK REGISTERS REGISTERS AND CONDITIONS EX/ST = 0 Standard Global Mask Message Center MEME = 0: Mask register ignored. ID and Standard 11-bit Registers 0–1 (Located in Arbitration Registers 0–1...
  • Page 83: Bit Timing

    SWINT bit when TSEG1 and TSEG2 are both cleared to 0. 1-Wire Bus Master The DS80C400 incorporates a 1-Wire bus master to support communication to external 1-Wire devices. The bus master provides complete control of the 1-Wire bus and coordinates transmit (Tx)/receive (Rx) activities with minimal supervision by the CPU.
  • Page 84: Clock Control

    DS80C400 Network Microcontroller Clock Control All 1-Wire timing patterns are generated using a base clock of 1.0MHz. To create this base clock frequency for the 1-Wire bus master, the microcontroller system clock must be internally divided down. The clock divisor internal register implements bits to control this clock division and generation.
  • Page 85 ROM pass. Details about the search ROM algorithm can be found in The Book of iButton Standards or the High- Speed Microcontroller User’s Guide: DS80C400 Supplement. FOW (Bit 2): Force OW Line Low. Setting this bit to logic 1 forces the OW line to a low value if the EN_FOW bit in the control register is also set to logic 1.
  • Page 86 DS80C400 Network Microcontroller EN_FOW (Bit 2): Enable Force OW. Setting the EN_FOW bit to a logic 1 allows the bus master to force the OW line low using FOW (bit 2 of the command register). Clearing the EN_FOW bit to a logic 0 disables the use of the FOW bit.
  • Page 87: Serial Ports

    The DS80C400 provides several of the most commonly needed peripheral functions in microcomputer-based systems. The DS80C400 offers three serial ports, four timers, a programmable watchdog timer, power-fail reset detection, and a power-fail interrupt flag. In addition, the microcontroller contains a CAN module for industrial communication applications.
  • Page 88: Watchdog Timer

    DS80C400 Network Microcontroller Timers The microcontroller provides four general-purpose timer/counters. Timers 0, 1, and 3 have three common modes of operation. Each of the three can be used as a 13-bit timer/counter, 16-bit timer/counter, or 8-bit timer/counter with auto-reload. Timer 0 can also operate as two 8-bit timer/counters. When operated as a counter, timers 0, 1, and 3 count pulses on the corresponding T0, T1, and T3 external pins.
  • Page 89 WD1:0 = 11 IrDA Clock The DS80C400 has the ability to generate an output clock (CLKO) as a secondary function on port pin P3.5. Setting both the IrDA clock-output enable bit (IRDACK:COR.7) and external clock-output enable bit (XCLKOE:COR.1) to a logic 1 produces an output clock of 16 times the programmed baud rate for serial port 0.
  • Page 90 1-Wire bus master Interrupt flag register are accessed in the same way. One’s Complement Adder The DS80C400 implements a one’s complement adder to support the Internet checksum algorithm. The adder contains a 16-bit accumulator and is accessed through the one’s complement adder data (OCAD) SFR.
  • Page 91: System Clock Control

    0000h. Clock Control and Power Management The DS80C400 includes a number of unique features that allow flexibility in selecting system clock sources and operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a clock multiplier is included in the microcontroller’s clock circuit. Also, in addition to the standard 80C32 idle and power- down (stop) modes, the DS80C400 provides a PMM.
  • Page 92 DS80C400 Network Microcontroller Changing the System Clock/Machine Cycle Clock Frequency The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the internal clock signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-4) state. For example, to change from 00 (frequency multiplier) to 11 (PMM), the software must change the bits in the following sequence: 00b =>...
  • Page 93: Oscillator-Fail Detect

    DS80C400 Network Microcontroller Status The STATUS (C5h) register and STATUS1 (F7h) register provide information about interrupt and serial port activity to assist in determining if it is possible to enter PMM. The microcontroller supports three levels of interrupt priority: power-fail, high, and low. The PIP (power-fail priority interrupt status; STATUS.7), HIP (high priority interrupt status;...
  • Page 94: Stop Mode

    Oscillator-Fail Detect 65,536 t (as described in Power Cycle Timing Characteristics) Note: When connecting the DS80C400 to an external PHY, do not connect the RSTOL to the reset of the PHY. Doing so may disable the Ethernet transmit. Idle Mode Setting the IDLE bit (PCON.0) invokes the idle mode.
  • Page 95: Pin Configuration

    Software Breakpoint Mode The DS80C400 provides a special software-breakpoint mode for code-debug purposes. Breakpoint mode can be enabled by setting the BPME bit (ACON.4) to a logic 1. Once enabled, the A5h op code can be used to create a break in code execution.
  • Page 96: Package Information

    Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

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