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Koheron Alpha250 User Manual

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Alpha250 User Guide
Koheron Alpha250 250 MSPS acquisition board

Getting started

Warnings
The Alpha250 power supply must be turned off before connecting or disconnecting:
the micro-SD card
peripherals on the expansion connector
Turn on the board
First, insert the micro-SD card into the micro-SD slot. Then connect the 12V jack of
the power supply. The power good green LED (PWGD) and the FPGA done orange
LED (DONE) indicate the system has correctly started.
Communicating with the board
LAN
The ethernet port is the main communication interface with the Alpha250. It can be
connected to a local network
the IP address are displayed on the 8 user LEDs.
Serial interface
The serial UART debugging interface can be accessed by the micro USB connector.
via a router
or
directly to a
www.koheron.com
computer. The last 8 bits of
1 / 13

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Summary of Contents for Koheron Alpha250

  • Page 1: Getting Started

    The power good green LED (PWGD) and the FPGA done orange LED (DONE) indicate the system has correctly started. Communicating with the board The ethernet port is the main communication interface with the Alpha250. It can be connected to a local network via a router directly to a computer.

  • Page 2: Micro Usb

    The external supply connector is a jack with 1.95 mm center pin and 6 mm outer diameter. Only 12 V must be supplied on this connector. Running the Alpha250 requires at least 1 A. More current may be required depending on the load on the expansion connector.

  • Page 3: Microsd Card

    PS core via a level-shifter. The SD card I/Os are ESD protected. Expansion connector Alpha250 expansion connector It contains: Power supplies. 12 V from external supply. 5 V up to 1 A (shared with USB 2.0 connector). + 3.3 V up to 800 mA, sequenced with I/Os supply. - 3.3 V up to 500 mA.
  • Page 4 50 Ω output impedance source. The peak-peak input range is 1 V (between -500 and 500 mV). The inputs are protected by a transient voltage suppressor clamping over-voltages beyond ± 8 V. Alpha250 RF ADC interface. The encoding clock of the ADC is provided by the of the clocking system. RF_ADC_CLK The output data are interfaced to the I/O Bank 34 of the FPGA.
  • Page 5 DAC gain on the configuration SPI bus. In the default configuration, the DAC outputs in a 50 Ω load. Alpha250 RF DAC interface. The sampling clock of the DAC is provided by the of the clocking system. RF_DAC_CLK The input data lines are interfaced to the I/O Bank 35 of the FPGA. It consists of 32 single-ended lines at 3.3 V.
  • Page 6 AD7124-8). The inputs differential pairs can be used to sense either floating or ground referenced signal. They also facilitate Kelvin sense connections. Differential input voltage range is ± 1.25 V. Alpha250 Precision ADC interface. The first four channels are available on the expansion connector.

  • Page 7: Temperature Sensors

    Temperature sensors The Alpha250 has two high-accuracy temperature sensors (TMP116) with an accuracy of ± 0.2 °C over -10 °C to +85 °C. One sensor is placed near the voltage reference (T0 highlighted in blue) to allow temperature compensation in high precision measurements.
  • Page 8 I2C0 The EEPROM is divided into two parts. The lower addresses are used by Koheron to store identification and calibration data. The higher addresses (above 0x1000) are for user applications. The EEPROM map addressing is given in the table below.
  • Page 9 DRIVE 8 [get_ports dac_*] # Channel 0 set_property PACKAGE_PIN D18 [get_ports {dac_0[0]}] set_property PACKAGE_PIN E17 [get_ports {dac_0[1]}] set_property PACKAGE_PIN E19 [get_ports {dac_0[2]}] set_property PACKAGE_PIN E18 [get_ports {dac_0[3]}] set_property PACKAGE_PIN A20 [get_ports {dac_0[4]}] set_property PACKAGE_PIN B19 [get_ports {dac_0[5]}] 9 / 13 www.koheron.com...
  • Page 10 # Configuration SPI (Bank 34) set_property IOSTANDARD LVCMOS18 [get_ports spi_cfg_*] set_property PACKAGE_PIN R17 [get_ports spi_cfg_sdo] set_property PACKAGE_PIN R16 [get_ports spi_cfg_sdi] set_property PACKAGE_PIN W16 [get_ports spi_cfg_sck] set_property PACKAGE_PIN V16 [get_ports spi_cfg_cs_rf_adc] set_property PACKAGE_PIN U12 [get_ports spi_cfg_cs_rf_dac] set_property PACKAGE_PIN T12 [get_ports spi_cfg_cs_clk_gen] 10 / 13 www.koheron.com...
  • Page 11 PL I/Os on bank 34. Precision ADC SPI bus. Constraint file The precision ADC SPI pins are connected to the Bank 34 with 1.8 V LVCMOS signals. # Precision ADC (Bank 34) set_property IOSTANDARD LVCMOS18 [get_ports spi_precision_adc_*] 11 / 13 www.koheron.com...
  • Page 12 Verilog. It is controlled with the PrecisionDac driver. PS cores The processing system contains hard cores (by opposition with the soft cores that can be deployed on the PL). The PS cores are interfaced with MIO pins on Bank 0. 12 / 13 www.koheron.com...
  • Page 13 The constraints file for the PS is: set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] I2C0 This bus is used on the Alpha250 internally and is not accessible from the expansion connector. The I2C0 bus addressing is: : Secure EEPROM 1100100 / 1011100...

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