Koheron Alpha250 User Manual
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Koheron Alpha250 User Manual

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Alpha250 User Guide
PDF version (https://s3-eu-west-1.amazonaws.com/koheronalpha250-public/koheron_alpha250_user_guide.pdf)
Koheron Alpha250 250 MSPS acquisition board (/fpga/alpha250-signal-acquisition-generation)

Getting started

Warnings
The Alpha250 power supply must be turned off before connecting or disconnecting:
the micro-SD card
peripherals on the expansion connector
Turn on the board
First, insert the micro-SD card into the micro-SD slot. Then connect the 12V jack of the power supply. The power good green LED
(PWGD) and the FPGA done orange LED (DONE) indicate the system has correctly started.
Communicating with the board
LAN
The ethernet port is the main communication interface with the Alpha250. It can be connected to a local network via a router
(/support/tutorials/ nd-dynamic-ip) or directly to a computer (/support/tutorials/setup-direct-ethernet-static-ip). The last 8 bits of
the IP address are displayed on the 8 user LEDs.
Serial interface
The serial UART debugging interface can be accessed by the micro USB connector. The required steps are described here
(/support/tutorials/setup-usb-serial-connection).
Connectors

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Summary of Contents for Koheron Alpha250

  • Page 1: Getting Started

    (PWGD) and the FPGA done orange LED (DONE) indicate the system has correctly started. Communicating with the board The ethernet port is the main communication interface with the Alpha250. It can be connected to a local network via a router (/support/tutorials/ nd-dynamic-ip) or directly to a computer (/support/tutorials/setup-direct-ethernet-static-ip). The last 8 bits of the IP address are displayed on the 8 user LEDs.

  • Page 2: Gigabit Ethernet

    The external supply connector is a jack with 1.95 mm center pin and 6 mm outer diameter. Only 12 V must be supplied on this connector. Running the Alpha250 requires at least 1 A. More current may be required depending on the load on the expansion connector.

  • Page 3: Expansion Connector

    PS core via a level-shifter. The SD card I/Os are ESD protected. Expansion connector Alpha250 expansion connector It contains: Power supplies. 12 V from external supply. 5 V up to 1 A (shared with USB 2.0 connector). + 3.3 V up to 800 mA, sequenced with I/Os supply.
  • Page 4 50 Ω output impedance source. The peak-peak input range is 1 V (between -500 and 500 mV). The inputs are protected by a transient voltage suppressor clamping over-voltages beyond ± 8 V. Alpha250 RF ADC interface. The encoding clock of the ADC is provided by the of the clocking system.
  • Page 5 LVDS signal. RF_DAC_CLK is an LVDS input clock on the FPGA. FPGA_CLK_IN are LVDS clocks available on the expansion connector. EXP_CLK0 EXP_CLK1 The clock generator is con gured by the con guration SPI bus via the ClockGenerator driver (https://github.com/Koheron/koheron- sdk/blob/master/boards/alpha250/drivers/clock-generator.hpp).

  • Page 6: Temperature Sensors

    Temperature sensors The Alpha250 has two high-accuracy temperature sensors (TMP116 (http://www.ti.com/lit/ds/symlink/tmp116.pdf)) with an accuracy of ± 0.2 °C over -10 °C to +85 °C. One sensor is placed near the voltage reference (T0 highlighted in blue) to allow temperature compensation in high precision measurements. The other one is placed between the clock generator and the RF ADC...
  • Page 7 (https://github.com/Koheron/koheron-sdk/blob/master/boards/alpha250/drivers/eeprom.hpp). The EEPROM is divided into two parts. The lower addresses are used by Koheron to store identi cation and calibration data. The higher addresses (above 0x1000) are for user applications. The EEPROM map addressing is given in the table below.
  • Page 8 The Zynq XC7Z020-2CLG400I has 2 I/O banks for the programmable logic (Banks 34 and 35) with 48 IOs each. One bank (Bank 0) is dedicated to the processing system with a multiplexed I/O (MIO) interface. The set of peripherals and interface buses is depicted below. Zynq peripherals and communication buses. I/O constraints are de ned in the ports.xdc le (https://github.com/Koheron/koheron- sdk/blob/master/boards/alpha250/con g/ports.xdc).
  • Page 9 RF ADC parallel bus The RF ADC is interfaced to the Bank 34 by a LVDS parallel bus. The data for each ADC channel are transferred in double data rate on a 7 line sub-bus. The RF ADC also provides a clock synchronous with the output data .
  • Page 10 # RF DAC (Bank 35) set_property IOSTANDARD LVCMOS33 [get_ports dac_*] set_property DRIVE 8 [get_ports dac_*] set_property IOSTANDARD LVCMOS33 [get_ports dac_*] set_property DRIVE 8 [get_ports dac_*] # Channel 0 set_property PACKAGE_PIN D18 [get_ports {dac_0[0]}] set_property PACKAGE_PIN E17 [get_ports {dac_0[1]}] set_property PACKAGE_PIN E19 [get_ports {dac_0[2]}] set_property PACKAGE_PIN E18 [get_ports {dac_0[3]}] set_property PACKAGE_PIN A20 [get_ports {dac_0[4]}] set_property PACKAGE_PIN B19 [get_ports {dac_0[5]}]...
  • Page 11 The s_axis_tdata s_axis_tvalid core is controlled via the SpiCon g driver (https://github.com/Koheron/koheron-sdk/tree/master/boards/alpha250/drivers/spi- con g.hpp). Precision ADC SPI bus A dedicated SPI is used for the communication with the precision ADC. The bus is connected to PL I/Os on bank 34.
  • Page 12 . The data will be synchronously updated if ldac = 1. If = 3, the output is updated as new values arrive. The core (https://github.com/Koheron/koheron- sdk/tree/master/boards/alpha250/cores/precision_dac_v1_0) is written in Verilog. It is controlled with the PrecisionDac driver (https://github.com/Koheron/koheron-sdk/tree/master/boards/alpha250/drivers/precision-dac.hpp). PS cores The processing system contains hard cores (by opposition with the soft cores that can be deployed on the PL).
  • Page 13 The constraints le for the PS is: set_property CFGBVS GND [current_design] set_property CONFIG_VOLTAGE 1.8 [current_design] I2C0 This bus is used on the Alpha250 internally and is not accessible from the expansion connector. The I2C0 bus addressing is: : Secure EEPROM 1100100 / 1011100 : RTC registers...

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