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A3A9 TRACK AND HOLD
85662-60165
( S E R I A L PREFIX:
2 5 4 1 A )
PIN
1
19
2
20
3
21
4
22
5
23
6
24
7
25
8
26
9
27
10
28
11
29
12
30
13
31
14
32
15
33
16
34
17
35
18
36
S1GNAL
NC
NC
NC
NC
NC
NC
ADC CND
ADC GND
VIDEO
ADC GND
ADC GND
ADC GND
NC
NC
NC
NC
NC
NC
LTRK
NC
NC
NC
INSEL B
RSEN
INSEL A
HSWP
NC
NC
HOLD
NC
DGND
DGND
+5V
NC
+15V
-15V
TO/FROM
A3A8P1-19
A3A8P1-21
A3A6P1-6
A3A6P1-12
A3A6P1-23
A3A1P1-21
A3A6P1-7
FUNCTION
BLOCK
F
F
E
F
F
F
C
C
c
c
c
c
F
F
F
F
F
LTRK
1
(D TRACK AND HOLD
+5YF
R56
1071
9090
— W S r —
-15YF
.. R54
A R55
<•
1
r
,
;
:
19.6K? 19.6K
jfcjj]
-15VF1 -15VFi
-15VF4 V
C16
.1
P1-5
VIDEO
n;
J
BIAS CHECK
TEST CONDITIONS ASSUME THE FOLLOWING
INSTRUMENT CONTROL SETT INGS:
I NSTRUMENT PRESET
CENTER FREQUENCY
20MHz
FREQUENCY SPAN
OHz
ATTENUATION
OdB
SINGLE SWEEP
N O T E S :
1. REFERENCE DESIGNATORS WITHIN
THIS ASSEMBLY ARE ABBREVIATED.
FOR COMPLETE REFERENCE
DESIG-
NATI ON,PREFIX ABBREVIATION WITH
ASSEMBLY
DESIGNATION.
2. UNLESS OTHERWISE
INDICATED:
RESISTANCE
IS IN OHMS (ft)
CAPACITANCE
IS IN MICROFARADS( uF )
INDUCTANCE
IS IN MICROHENRIES( pH)
3. UNLESS OTHERWISE INDICATED:
LOGIC LEVELS ARE TTL:
+2.OV TO +5.OV-LOGIC ' 1' -HIGH
OV TO +0.8V=L0GIC '0' =LOW
4.
MNEMONIC TABLE:
MNEMONIC
INSEL A
INSEL B
RSEN
HSWP
HOLD
OFS POS
GPOS
OFS NEG
GNEG
T/H GAIN
(T/H) OFS
LTRK
DESCRIPTION
MULTIPLEX CHANNEL SELECT
MULT IPLEX CHANNEL SELECT
PEAK DETECTOR RESET
ENABLE
HIGH-SWEEPING
SAMPLER ON/OFF CONTROL
OFFSET POSIT I \E PEAK
DETECTOR
GAIN POS ITIVE PEAK
DETECTOR
OFFSET NEGATIVE PEAK
DETECTOR
GA IN NEGATI YE PEAK
DETECTOR
TRACK AND HOLD GAIN
ADJUST
TRACK AND HOLD OFFSET
ADJUST
TRACKING INPUT SIGNAL
5.
INPUT SELECT TABLE
INSEL A
0
1
0
1
INSEL B
0
0
1
1
FUNCTIOf
SELECTEE
SAMPLE
POS PEAK
NEG PEAK
POS PEAK
GROUNDING LNOISE FORCES LTRK HIGH,
INDICATING A 'NOISY' SIGNAL. THIS
IS DONE TO CHECK DYNAMIC TRACKING
OF PEAK DETECTORS.
Q1,2,3,7,8,10AND 16 ARE DUAL
TRANSISTORS WITH THE FOLLOWING
PIN CONFIGURATION.
TOP VIEW
EG?' "TCI E
06 AND Q14 ARE MOS n-ohannel ENHANCE
MENT MODE FETs WITH THE FOLLOWING
PI N CONF IGURATI ON:
TOP VIEW
9. 04,11, AND 13 ARE DUAL FETe WITH THE
FOLLOWING PIN CONFIGURATION:
TOP VIEW
s
l E T
""SG2
Dl <D
Q) S
2
S i V J2>l°2
TP3
2.00V
U1 PIN 1
.98V
U1 PIN 9 TP 9
.98Y
10Y
U1 PIN 4
.98V
_ ]
UNLESS OTHERWISE INDICATED:
SIGNALS ENTER AT LEFT SIDE OR TOP AND EXIT
AT RIGHT SIDE OR BOTTOM OF FUNCTION BLOCKS.
A 3 A 9
A 3 A 9
T R A C K
A N D H O L D , S C H E M A T I C
D I A G R A M
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