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Test Circuit
The test circuit on A3A8 is designed to aid in troubleshooting lower-order bit failures and
linearity problems in both the Ramp Converter circuit and the ADC circuit. The test circuit
is normally transparent to A3A8 operation, and is activated by grounding A3A8TP8 NOISE
TEST or A3A8TP10 RAMP TEST to A3A8TP9 to switch multiplexers U16, U17, and U18.
Noise Test
The Noise Test, activated by grounding A3A8TP8 NOISE TEST to A3A8TP9, "expands"
the vertical scale of the Digital Storage Section for closer examination of digital data from
the ADC circuit. This is accomplished by shifting the 4 least significant bits (LSBs) of
the digitized video data by 6 bits, effectively multiplying it by 64. When the noise test is
activated, the 6 most significant bits (MSBs) are not used, and the 6 LSBs are forced to logic
0. In addition, the "new" MSB is inverted to center the CRT trace (assuming the VIDEO
input signal was at top-screen). The resulting CRT trace appears to be amplified to 64 times
the normal resolution allowing variations in the LSBs to be easily viewed.
With the noise test activated, a constant VIDEO signal present at the input to A3A9 Track
and Hold will ideally produce a flat CRT trace. The CRT trace should exhibit no more than 2
bits peak-to-peak of digital noise.
Stuck ADC bits and transistor noise on A3A8 can be easily checked in the noise test mode by
removing A3A9 Track and Hold from the instrument and jumpering A3A8TP2 SWP/100 to
A3A8TP6 VIDEO. This substitutes a scaled-down sweep ramp signal for the VIDEO input
signal to the ADC. A series of approximately 10 stair-steps should be displayed on the CRT,
each with sharp, well-defined corners.
The noise test mode can be used to adjust the peak detector offsets (OFS POS and OFS
NEG) on A3A9 Track and Hold by grounding A3A9TP3 to A3A9TP1, with the VIDEO cable
(96) disconnected from A3A9J1. The CRT trace will fall on the bottom graticule line when
both offsets on A3A9 are properly adjusted.
Ramp Test
The Ramp test is very similar to the Noise Test, and is activated by grounding A3A8TP10
RAMP TEST to A3A8TP9. In addition, the VIDEO cable (96) is disconnected from A3A9J1,
and A3A8TP1 SWP is jumpered to A3A9TP3 to substitute the sweep ramp signal as the
VIDEO input to A3A9 Track and Hold. In the ramp test mode, the test circuit again
"expands" the vertical CRT scale by a factor of 64. The 4 LSBs of digital scan data are
subtracted from the 4 LSBs of digitized video data, and the results are displayed on the CRT.
Since both sets of digital data correspond to the sweep ramp voltage, the subtraction ideally
yields a constant value (011100000=448). If the Track and Hold, ADC, and Ramp Converter
circuits are linear and functioning properly, a horizontal line will appear approximately
1/2-division below the center CRT graticule line. This line might exhibit numerous noise-like
spikes in peak-detector mode, which is normal.
Linearity and noise in the Ramp Converter, ADC, and Track and Hold circuits can also be
checked without using the ramp test. As before, disconnect the VIDEO cable (96) from
A3A9J1 and jumper A3A8TP1 SWP to A3A9TP3. This substitutes the sweep ramp signal as
the VIDEO input to A3A9 Track and Hold. A straight diagonal line should be displayed on
the CRT, indicating linear digitizing of the analog sweep ramp signal by both the ADC and
the Ramp Converter circuits.
6 A3A8
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Table of Contents
Troubleshooting
