Related Manuals for Active-semi PAC5532EVK1
Summary of Contents for Active-semi PAC5532EVK1
- Page 1 PAC5532EVK1 User’s Guide Power Application Controllers www.active-semi.com Copyright © 2018 Active-Semi, Inc.
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Page 2: Table Of Contents
SWD Debugging ...............................7 JTAG Debugging ..............................7 Serial Communications .............................7 Alternate Serial Communications ........................8 Hall Sensor / DAC Interface ..........................8 PAC5532EVK1 Setup ............................10 Power Considerations ............................11 Maximum Current and Voltage ........................11 SENSE Resistors ............................11 Power FETs ..............................11 Increasing Output Power (Appendix) ........................ -
Page 3: Overview
(MCU) and all the necessary circuitry to properly energize the MCU and its internal peripherals once power is applied. To aid in the application development, the PAC5532EVK1 offers access to each and every one of the PAC5532 device’s signals by means of a series of male header connectors. - Page 4 GPIO. Gate driving for up to three half H Bridge (tri phase) inverter. • Schematics, BOM, Layout drawings available • The following sections provide information about the hardware features of Active-Semi’s PAC5532EVK1 turnkey solution. Rev 1.0 February 2018...
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Page 5: Pac5532Evk1 Resources
PAC5532EVK1 R ESOURCES Pinout and Signal Connectivity The following diagram shows the male header pinout for the PAC5532EVK1 evaluation module, as seen from above: Figure 2 PAC5532EVK1 Headers and Test Stakes Pinout Rev 1.0 February 2018... -
Page 6: Power Input
Power Input Power to the PAC5532EVK1 evaluation module can be applied to the VIN and GND spade connectors. Said applied power should not exceed 160V (Abs Max). The PAC5532EVK1 is optimized to operate with voltages ranging from 25V to 120V Nominal (160V Abs Max). -
Page 7: Swd Debugging
SWD Debugging Connector J3 offers access to the PAC5532 SWD port lines. J3 Pin Terminal Description VCCIO (default is 3.3V) SWD Serial Data SWD Serial Clock GND (System Ground) JTAG Debugging Connector J13 is a standard MIPI20 offering access to the JTAG port as well as single data line TRACE debug. -
Page 8: Alternate Serial Communications
Alternate Serial Communications When enabled, connector J14 provides access to a secondary UART port lines. J14 Pin Terminal Description VCCIO (default is 3.3V) MCU Transmit Line (PF3 – requires 0 ohm resistor R41 to be populated) MCU Receive Line (PF2) GND (System Ground) Hall Sensor / DAC Interface Connector J12 offers access to the PAC5532 resources on PORTD utilized for hall sensor based... - Page 9 NOTE: Test stakes DAC1/2/3 are only available when jumpers JMP1/2/3 have been shunted on the DAC respective position Test Stake Description DAC 1 PORTD0 DAC 2 PORTD1 DAC 3 PORTD2 Rev 1.0 February 2018...
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Page 10: Pac5532Evk1 Setup
PAC5532EVK1 S ETUP The setup for the PAC5532EVK1 evaluation module requires up to four simple connections. 1. Connect the VIN power source via spade tab connectors VIN and GND. As VIN power is applied, the LED D17 will light up. Once VIN voltage goes above 25V, the PAC5532’s Multi Mode Power Manager will be engaged and the VSYS (5V) regulator will be enabled. -
Page 11: Power Considerations
The SENSE resistors utilized to digitize motor winding current will determine how much current the three phase inverter will be able to handle. The PAC5532EVK1 module ships with 0.01 Ohm 3W SENSE resistors. For higher current handling, a smaller SENSE resistor could be employed. -
Page 12: Increasing Output Power
NCREASING UTPUT OWER PPENDIX In this section we provide different techniques which must be employed when wanting to drive higher then 10A per phase loads. As depicted in previous sections, the user will be responsible for selecting a proper SENSE resistor, suitable power FET, adding heat sinking and in some cases, some extra clamping. Suggested Heat Sink Profile The following drawing offers guidelines for a shape which could be utilized to fabricate a heat radiator. -
Page 13: Clamping Mechanisms
PAC5532 pre drive power stage block. Adding DRS Clamps The PAC5532EVK1 evaluation module already incorporates a series of clamps put in place to protect the DRSx terminal from negative transients at the phase outputs. However, under high current scenarios, it is plausible to see large positive transients. -
Page 14: About Active-Semi
Active-Semi product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Active-Semi accepts no liability for inclusion and/or use of its products in such equipment or applications. Active-Semi does not assume any liability arising out of the use of any product, circuit, or any information described in this document.