Sharp LC-32SV40U Service Manual page 58

11. LVDS, mini-LVDS (option), EPI (option)
1.2. U3101 (
NT5CB64M16DP
Description
The 1Gb Double-Data-Rate-3 (DDR3/L) B-die DRAMs is double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices. These synchronous
devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3/L DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential
clocks (CK rising and ___falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a
source
synchronous fashion. These devices operate with a single 1.5V ± 0.075V &1.35V -0.067/+0.1V power supply and
are available in BGA packages.
The DDR3/L SDRAM D-Die is a high-speed dynamic random access memory internally configured as an eight-bank
DRAM. The DDR3/L SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch
architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write operation for the DDR3/L SDRAM consists of a single 8n-bit wide, four clock data transfer at the
internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3/L SDRAM are burst oriented, start at a selected location, and continue for a
burst length of eight or a 'chopped' burst of four in a programmed sequence. Operation begins with the registration of
an Active command, which is then followed by a Read or Write command. The address bits registered coincident
with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A13
select the row). The address bit registered coincident with the Read or Write command are used to select the
starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10),
and select BC4 or BL8 mode 'on the fly' (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3/L SDRAM must be powered up and initialized in a predefined manner. The
following sections provide detailed information covering device reset and initialization, register definition, command
descriptions and device operation.
1.3. U6102 (YAMAHA YDA175)
Features
・Supply Voltage Range V
・Input Digital Audio Interface (Stereo)
Sampling Frequency: 32kHz, 44.1kHz, 48kHz
Left-justified, MSB first, 1-bit delay, Digital Audio Data 24-bits
・Max. Instantaneous Output 15W×2ch (V
10W×2ch (V =12V, R
DDP
10W×2ch (V =12V, R
DDP
)
5V to 18V
DDP *1)
=15V, R
DDP
=8Ω, THD+N=10%)
L
=6Ω, THD+N=10%)
L
=8Ω, THD+N=10%)
L
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