Siemens Simatic S7-1500 Function Manual page 49

Event-driven program execution
4.1 Response time of the CPUs when program execution is event-controlled
Interrupt response times of the CPUs for hardware interrupts
The interrupt response time starts with the occurrence of a hardware interrupt event in the
CPU. The interrupt response time ends with the start of processing of the assigned hardware
interrupt OB.
This time is subject to system-inherent fluctuations, and this is expressed using a minimum
and maximum interrupt response time.
The following table contains the length of the typical response times of the CPUs for
hardware interrupts.
Table 4- 1 Response times of the CPUs for hardware interrupts
Interrupt re- Min.
sponse times
Max.
Interrupt re- Min.
sponse times
Max.
* Additional information about cycle and response times of R/H CPUs is available in the section "Cycle and response times
of the S7-1500R/H redundant system"
Interrupt re- Min.
sponse times
Max.
Interrupt re-
sponse times
The specified times are extended:
● If higher-priority interrupts are queued for execution
● If the hardware interrupt OB is assigned to a process image partition
48
1511(F)-1 PN 1515(F)-2 PN
1511T(F)-1 PN 1515T(F)-2 PN
1511C-1 PN 1516(F)-3 PN/DP
1512C-1 PN 1516T(F)-3 PN/DP
1513(F)-1 PN
100 μs 90 μs
400 μs 360 μs
1513R-1 PN
100 μs
400 μs
1510SP(F)-1 PN
100 μs
400 μs
Min.
Max.
S7-1500
1517(F)-3 PN/DP
1517T(F)-3 PN/DP
30 μs
120 μs
S7-1500R/H* in RUN-Solo system state
1515R-2 PN
90 μs
360 μs
ET 200SP
1512SP(F)-1 PN
100 μs
400 μs
1516pro(F)-2 PN
1518(F)-4 PN/DP
1518(F)-4 PN/DP MFP
20 μs
90 μs
CPU 1517H-3 PN
30 μs
120 μs
1515SP(F)-PC
90 μs
360 μs
ET 200pro
90 μs
360 μs
Cycle and response times
Function Manual, 10/2018, A5E03461504-AD