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Related Manuals for Alphi IP-FASTDAC
Summary of Contents for Alphi IP-FASTDAC
- Page 1 8 channel 16 bit 2uS Digital to Ananlog Converter With 4 Quadrant Multiplier Industry Pack Module REFERENCE MANUAL 801-10-000-4000 Version 1.0 June 2003 ALPHI TECHNOLOGY CORPORATION 6202 S. Maple Avenue #120 Tempe, AZ 85283 USA Tel: (480) 838-2428 Fax: (480) 838-4477...
- Page 2 ALPHI TECHNOLOGY reserves the right to make any changes, without notice, to this or any of ALPHI TECHNOLOGY’s products to improve reliability, performance, function or design.
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Page 3: Table Of Contents
IOSPACE ____________________________________________________________________ 3 2.1.3 INTSPACE ___________________________________________________________________ 4 2.1.4 Memory space ________________________________________________________________ 4 ANALOG OUTPUT ______________________________________________________ 4 JUMPER SETTINGS ___________________________________________________6 JUMPER LOCATION___________________________________________________6 Vref BLOCK DIAGRAM_________________________________________________6 OUTPUT CONNECTOR_________________________________________________7 ALPHI TECHNOLOGY CORP. Page iii REV 1.0 Part Number : 801-10-00-4000 Copyright ALPHI Technology Corporation, 2000... -
Page 4: General Description
A functional block diagram of the IP-FASTDAC is presented below in Figure 1-1. The IP-FASTDAC operates as a slave that is managed by the host processor on the IP bus. The IP-FASTDAC is supported by ALPHI Technology under Windows NT by a Board Support Package which is supplied with the card. -
Page 5: Internal Organization
IP-FASTDAC REFERENCE MANUAL 2. INTERNAL ORGANIZATION The IP-FASTDAC card is divided into different sections. Each section and its relationship to other sections will be discussed. The IP-FASTDAC sections are: • IP interface • Analog Output 2.1 IP INTERFACE 2.1.1 IDSPACE An EEPROM memory that occupies 2 Kbytes of address space is for providing information about the module to the user. -
Page 6: Iospace
2.1.2 IOSPACE 2.1.2.1 LOCAL REGISTERS The IP-FASTDAC module uses 8 - LTC1821 Ultra precise fast setting V-out D/A converters from Linear Technology. A double buffered interface is used to transfer incoming data to the output. The first 8 ($00 - $0E) addresses are used to pre-load data into the first stage of each D/A converter. -
Page 7: Intspace
The on board EEPROM provides 2K – 32bytes space available for the user. 2.2 ANALOG OUTPUT The IP-FASTDAC has eight analog outputs each with its own buffer. The outputs are +/- 10 Volts. LTC 1821 (16bit Ultra Precise, Fast Settling Vout DAC) - Page 8 0000 0000 0000 0000 - Vref OUTPUT BUFFER IP-FASTDAC can be configured with either a high speed, high output current (BUF634) or High speed, low offset voltage (OPA132) input buffers. The specs are below for each device. BUF634 ( 250mA High-Speed Input Buffer)
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Page 9: Jumper Settings
IP-FASTDAC REFERENCE MANUAL 3. JUMPER SETTINGS The IP-FASTDAC allows the possible of configuring each DAC channel for internal or external Vref supply. See chart below for configuration possibility. Factory default for Vref is internal +10 volts. A +5volt internal Vref can be accommodated upon request. -
Page 10: Output Connector
DAC # 5 AGND AGND AGND DAC # 6 AGND AGND VREFX7 VREFX8 AGND DAC # 7 AGND AGND AGND DAC # 8 AGND AGND ALPHI TECHNOLOGY CORP. Page 7 REV 1.0 Part Number : 801-10-00-4000 Copyright ALPHI Technology Corporation, 2000...
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