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Related Manuals for Alphi IP-48ADM16
Summary of Contents for Alphi IP-48ADM16
- Page 1 IP-48ADM16 High Density 48-channel, 16-bit A/D Converter REFERENCE MANUAL 833-13-000-4000 Version 1.3 December 2007 ALPHI TECHNOLOGY CORPORATION 6202 S. Maple Avenue #120 Tempe, AZ 85283 USA Tel: (480) 838-2428 Fax: (480) 838-4477...
- Page 2 ALPHI TECHNOLOGY does not assume any liability arising out of the application or use of any product or circuit described herein; nor does ALPHI TECHNOLOGY convey any license under its patent rights or the rights of others.
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Page 3: Table Of Contents
IRECT RESET ___________________________________________________________ 18 CONNECTORS ____________________________________________19 JUMPER DESCRIPTIONS ___________________________________19 CONNECTOR DESCRIPTIONS________________________________________ 20 APPLICATION EXAMPLE____________________________________21 HOW TO SET A CHANNEL AS AD TRIGGER. ___________________________ 21 ALPHI TECHNOLOGY CORP. Page iii REV 13 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... - Page 4 IP-48ADM16 HARDWARE REFERENCE MANUAL SINGLE CHANNEL CONVERSION CONTROLLED BY HOST _______________ 21 SCAN LIST CONVERTED ONCE CONTROLLED BY HOST OR EXTERNAL TRIGGER _________________________________________________________ 21 ALPHI TECHNOLOGY CORP. Page iv REV 13 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000...
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Page 5: General Description
• On board input switches for offset or gain calibration • Dual threshold level detection for each channel with interrupt possibilities • Analog trigger with any channel and level selection ALPHI TECHNOLOGY CORP. Page 1 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 6: Functional Description
FUNCTIONAL DESCRIPTION A data flow block diagram of the * is presented in Figure 1-1. The IP-48ADM16 has 6 fault-protected CMOS analog multiplexers. Each multiplexer has 8 inputs and one common output. These outputs are acquired by differential multiplexers. The differential inputs can then be configured for single-ended, differential, or calibration modes. -
Page 7: Theory Of Operation
1-2, 4-6, 9-10 0 -+10v 1-2, 3-5, 8-10 0 -+5v 1-2, 3-5, 9-10 0 -+2.5v 1-2, 5-7, 9-10 Note: J3 is factory use, do not change. ALPHI TECHNOLOGY CORP. Page 3 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 8: Single-Ended Mode
2.1.2 Differential Mode In differential mode channel #0 is associated with channel #24 and so on, until the channel #23 being associated to channel #47. ALPHI TECHNOLOGY CORP. Page 4 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 9: A/D Converter
More information is available at www.analogdevices.com. 2.2.1 Acquisition Mode Setting up the IP-48ADM16 for acquisition is done in several steps: 1) select the Scan clock source: • Internal with the internal timer (the divisor needs to be programmed as well. -
Page 10: Continuous Mode
Setting the DATARAM pointer with a desired address lower than the End address or a number of scan lower than the total scan and enabling an interrupt, the host can “throttle” the read of A/D data. ALPHI TECHNOLOGY CORP. Page 6 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 11: Interface To The Ip Carrier
3.2.1 Address Map MEMORY + BITS Register 0x00000-1FFFF R/W DataRAM 0x20000-2007F Channel List RAM 0x20080-200FF Threshold High RAM 0x20100-2017F Threshold Low RAM Table 3.2: Memory Map ALPHI TECHNOLOGY CORP. Page 7 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 12: Dataram
Allow interrupts in relation with the “Threshold High” value. See Table 2.2.2 for bit selection. Threshold low Allow interrupts in relation with the “Threshold High” value. See Table 2.2.2 for bit selection. ALPHI TECHNOLOGY CORP. Page 8 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... - Page 13 Calibration can be done by switching the two inputs of the differential amplifier to: GND OR +5V TO INPUT+ OR +5V TO Input, using pre-defined channels: ALPHI TECHNOLOGY CORP. Page 9 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000...
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Page 14: Threshold High Ram
#0, and so on, until the position 47 corresponding to channel #47. The locations 48 to 63 are not used. ALPHI TECHNOLOGY CORP. Page 10 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 15: Iospace
Channel Interrupt Register #1 (bit 16-31) 0x1C Channel Interrupt Register #2 (bit 32-47) 0x20 Status register 0x22 Reset Interrupt #0 0x24 A/D Register Table 3.3 IO Registers ALPHI TECHNOLOGY CORP. Page 11 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 16: Internal Clock Divisor (Icdh, Icdl)
Using the Count Type bit of the Trigger Register, this register can contain either a pointer value in the DataRAM or a number of reading sets. ALPHI TECHNOLOGY CORP. Page 12 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 17: Interrupt / Dma Source
When this bit is set, every new acquisition data available activates the DMARQ. The data should be read in the Direct A/D Read register. ALPHI TECHNOLOGY CORP. Page 13 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 18: Stop Acquisition Register
These 2 bits determine what event causes the state machine to start executing the channel list again. If the state machine is already busy, the trigger is ignored. ALPHI TECHNOLOGY CORP. Page 14 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 19: Trigger Register
If “0”, the scan list is activated and acquisition stops only at the end of the DataRAM memory. If “1”, the scan list is activated but stops when the condition that started the scan disappears. ALPHI TECHNOLOGY CORP. Page 15 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 20: Start Acquisition
Address: IOspace + 0x14 This 8-bit Interrupt Vector register can be programmed by the host. It will be output to during an interrupt acknowledge IP INTESELA access. ALPHI TECHNOLOGY CORP. Page 16 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 21: Digital Filter Register
BUSYIN INTREQ #0 INTREQ #0 This bit shows the state of the interrupt line # 0. Set to “0” when Start acquisition is generated. ALPHI TECHNOLOGY CORP. Page 17 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 22: Reset Interrupt Request #0
Address: IOspace + 0x24 This register contains the result of the latest A/D acquisition. RESET The * is reset when the IP carrier issues a reset. ALPHI TECHNOLOGY CORP. Page 18 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 23: Connectors
1-2 sets IN-48 on I/O P2 pin 49 and 2-3 setup Ex-Event on pin 49 Factory Use Factory Use 1-2 3-4 MSEL0 and MSEL1 for programming Cyclone EP1C12Q240. Table 5.1 Jumper Descriptions ALPHI TECHNOLOGY CORP. Page 19 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 24: Connector Descriptions
IN39/IN15- IN16/IN16+ IN40/IN16- IN17/IN17+ IN41/IN17- IN18/IN18+ IN42/IN18- IN19/IN19+ IN43/IN19- IN20/IN20+ IN44/IN20- IN21/IN21+ IN45/IN21- IN22/IN22+ IN46/IN22- IN23/IN23+ IN47/IN23- Table 5.2: IP External I/O Connector (P4) ALPHI TECHNOLOGY CORP. Page 20 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000... -
Page 25: Application Example
8-A/D conversion result is available at address zero of the DATARAM. SCAN LIST CONVERTED ONCE CONTROLLED BY HOST OR EXTERNAL TRIGGER Same a above but generate a scan-list with at the end channel $FF ALPHI TECHNOLOGY CORP. Page 21 REV 1.0 Copyright © 2007, ALPHI Technology Corporation Part Number: 833-13-000-4000...
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