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IDT 8A3 Series Programming Manual

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How to Use this Document
The 8A3xxxx Family Programming Guide contains information on how to access internal registers and what those registers do in detail for all
devices in the 8A3xxxx family. Not all devices in the family support all the same features or quantities of logic blocks, however the register
blocks all behave and are addressed at the same locations in all device. Some devices will not make use of all register blocks since the
associated feature or block of circuitry may not be available in that particular device. A Programming Guide Addendum for each specific device
will indicate which register modules are support in that device.
In addition, there are several other pieces of documentation that describe specific functions or details for the family or individual devices.
Table 1
shows related documents.
Table 1: Related Documentation for Devices in the 8A3xxx Family
Document Title
<device name> Datasheet
<device name>-<dash code> Datasheet Addendum
8A3xxxx Family Programming Guide (v4.7)
Evaluation Board Reference Manual
Timing Commander Personality User Manual
This document discusses the registers supported by a particular version of the Firmware (FW) running on the
internal micro-controller within the 8A3xxxx family of devices. Register maps may change between major releases
of the FW, so please check the
FW revision being used on the device. FW version numbering follows the format:
v<major release number>.<minor release number>.<hotfix number>
©2018 Integrated Device Technology, Inc
8A3xxxx Family Programming Guide
Revision History
Contains a functional overview of the device and hardware-design related details
including pinouts, AC & DC specifications and applications information related to
power filtering and terminations.
Indicates pre-programmed power-up / reset configurations of this specific 'dash
code' part number
Contains detailed register descriptions and address maps for all members of the
family of devices. Please check the <device name> datasheet to check the version
used by that device. All devices that use this version number use some subset of
this register map, as indicated in their device-specific Programming Guide
Addendum document..
Describes the Evaluation Board. Evaluation boards are available for the 8A34001
(144BGA) or 8A34002 (72QFN) devices. These devices contain a superset of the
functionality available in all other members of the 8A3xxxx Family. So they can
serve as evaluation tools for any of the less fully-featured family members.
Detailed description of how to use IDT's Timing Commander configuration tool. At
this time, a personality file is only available for 8A34001. This personality contains a
superset of the functionality available in all other members of the 8A3xxxx family.
Since all members of the 8A3xxxx family share register locations and resource
numbering, configurations generated using the 8A34001 personality can be used in
any member of the 8A3xxxx family. Functionality that is not available on the other
family members will of course not respond to any configuration of it that is made.
section of this document to ensure this document aligns with the
1
Document Description
8A3xxxx
v4.7
September 12, 2018

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Summary of Contents for IDT 8A3 Series

  • Page 1 Timing Commander Personality User Manual Detailed description of how to use IDT’s Timing Commander configuration tool. At this time, a personality file is only available for 8A34001. This personality contains a superset of the functionality available in all other members of the 8A3xxxx family.
  • Page 2 Register Set Descriptions - describes a set of registers that is made available for users to quickly and simply access the commonly-used features of the 8A3xxxx. ▪ Revision History ▪ IDT Contact information ©2018 Integrated Device Technology, Inc September 12, 2018...
  • Page 3 8A3xxxx Family Programming Guide Serial Port Overview The 8A3xxxx family supports up to 3 serial ports. One is a dedicated Master port used for loading configuration data at reset and the other two are configurable slave or SPI ports that can be used at any time after the reset sequence is complete to monitor and/or configure the device.
  • Page 4 8A3xxxx Family Programming Guide Figure 2: I C Slave Sequencing Diagram Sequential 8-bit Read Dev Addr + W Offset Addr X Dev Addr + R Data X Data X+1 Data X+n Sequential 8-bit Write Dev Addr + W Offset Addr X Data X Data X+1 Data X+n...
  • Page 5 8A3xxxx Family Programming Guide C 1B Mode Page Register Bit Field Descriptions Bit Field Name Field Type Default Value Description PAGE_ADDR[7:0] The values in this field are always replaced by the bits in I C transaction itself and so have no meaning. PAGE_ADDR[15:8] Select which register page to access.
  • Page 6 8A3xxxx Family Programming Guide Example read from register 0xC024 B6* FC 00 C0 10 20 #Set Page Register, *I C Address is left-shifted one bit. B6 24* #Set I C pointer to 0xC024, *I C instruction should use “No Stop” B7 <read back data>...
  • Page 7 8A3xxxx Family Programming Guide – In 1B operation, the 16-bit register address is formed by using the 7-bits of address supplied in the SPI access and taking the upper 9-bits from the page register.The page register is accessed, no matter what page the serial port is currently on, using an Offset Address of 7Ch - 7Fh.
  • Page 8 8A3xxxx Family Programming Guide Table 5: SPI 2B Mode Page Register Bit Field Locations and Descriptions Offset SPI 2B Mode Page Register Bit Field Locations Address (Hex) 7FFD PAGE_ADDR PAGE_ADDR[14:8] [15] 7FFE PAGE_ADDR[23:16] 7FFF PAGE_ADDR[31:24] 1. Burst access must begin at this non-aligned offset and all 3 bytes must be written in the same SPI burst access. A burst beginning at the 32-bit aligned address of 7FFCh will not correctly set this register.
  • Page 9 8A3xxxx Family Programming Guide Register Table Overview When programming an 8A3xxxx family device, it is necessary to read or write values to one or more ‘bit-fields’ within the device. A bit-field provides status and/or control information on a single aspect of a single feature. A bit field may be as small as a single-bit or many bytes in length.
  • Page 10 8A3xxxx Family Programming Guide A number of registers are grouped together into a module. In general a module contains all the registers needed to interact with a functional block within the device. Each module in the standard register set is listed in a Register Module Index table showing its module base address, a brief description of the module’s function and a link to that module’s location in the document.
  • Page 11 8A3xxxx Family Programming Guide The device contains multiple copies of many functional blocks and each will have its own associated register module for status and control. To keep the documentation clear and concise, only the first instance of a register module for a specific functional block will be shown in detail. The module table will show all instantiations of the module with their unique base addresses, but the links will all point to the same descriptive section (see blue arrows in Figure...
  • Page 12 8A3xxxx Family Programming Guide Terminology The following terminology and abbreviations are used in the register tables. If a bit-field has more than a single bit, the bit-field will be written as BIT_FIELD_NAME[msb:lsb] (e.g. DPLL_MANUAL_HOLDOVER_VALUE[39:0] Binary numbers will be written with a lowercase ‘b’ after them (e.g. 0101b ) Hexadecimal numbers will be written with a lowercase ‘h’...
  • Page 13 8A3xxxx Family Programming Guide Register Set Descriptions Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description 8180h Module: HW_REVISION Hardware Revision ID register C000h Module: RESET_CTRL General reset management. C014h Module: GENERAL_STATUS Chip hardware status registers. C03Ch Module: STATUS Live status of alarms and events.
  • Page 14 8A3xxxx Family Programming Guide Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description C290h INPUT_11 Input 11 configuration. Same as INPUT_0. C2A0h INPUT_12 Input 12 configuration. Same as INPUT_0. C2B0h INPUT_13 Input 13 configuration. Same as INPUT_0. C2C0h INPUT_14 Input 14 configuration.
  • Page 15 8A3xxxx Family Programming Guide Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description C3A4h REF_MON_15 Reference monitor 15. Same as REF_MON_0. C3B0h Module: DPLL_0 DPLL 0 configuration registers. C400h DPLL_1 DPLL 1 registers. Same as DPLL_0. C438h DPLL_2 DPLL 2 registers.
  • Page 16 8A3xxxx Family Programming Guide Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description C820h DPLL_PHASE_2 DPLL 2 write phase. Same as DPLL_PHASE_0. C824h DPLL_PHASE_3 DPLL 3 write phase. Same as DPLL_PHASE_0. C828h DPLL_PHASE_4 DPLL 4 write phase. Same as DPLL_PHASE_0.
  • Page 17 8A3xxxx Family Programming Guide Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description C8B0h DPLL_PHASE_PULL_IN_6 DPLL 6 phase pull-in control. Same as DPLL_PHASE_PULL_IN_0. C8B8h DPLL_PHASE_PULL_IN_7 DPLL 7 phase pull-in control. Same as DPLL_PHASE_PULL_IN_0. C8C0h Module: GPIO_CFG GPIO global configuration.
  • Page 18 8A3xxxx Family Programming Guide Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description CA24h OUTPUT_1 Output 1 register. Same as OUTPUT_0. CA34h OUTPUT_2 Output 2 register. Same as OUTPUT_0. CA44h OUTPUT_3 Output 3 register. Same as OUTPUT_0. CA54h OUTPUT_4 Output 4 register.
  • Page 19 8A3xxxx Family Programming Guide Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description CB48h PWM_DECODER_1 PWM 1 decoder registers. Same as PWM_DECODER_0. CB50h PWM_DECODER_2 PWM 2 decoder registers. Same as PWM_DECODER_0. CB58h PWM_DECODER_3 PWM 3 decoder registers. Same as PWM_DECODER_0.
  • Page 20 8A3xxxx Family Programming Guide Table 6: Register Set Module Index Module Base Address (Hex) Link Module Description CC10h TOD_WRITE_1 Write TOD 1 registers. Same as TOD_WRITE_0. CC20h TOD_WRITE_2 Write TOD 2 registers. Same as TOD_WRITE_0. CC30h TOD_WRITE_3 Write TOD 3 registers. Same as TOD_WRITE_0.
  • Page 21 Module: HW_REVISION Hardware Revision Information.Note that while this register can be accessed directly from the serial port by software, in IDT’s TIming Commander GUI tool, it must be accessed indirectly since it is located in the hardware only register space.
  • Page 22 8A3xxxx Family Programming Guide Table 9: RESET_CTRL Register Index Register Module Base Address: C000h Offset (Hex) Individual Register Name Register Description 00Ah RESERVED This register must not be modified from the read value 00Bh RESERVED This register must not be modified from the read value 00Ch RESERVED This register must not be modified from the read value...
  • Page 23 8A3xxxx Family Programming Guide Module: GENERAL_STATUS Notification for hardware status. Table 11: GENERAL_STATUS Register Index Register Module Base Address: C014h Offset (Hex) Individual Register Name Register Description 000h RESERVED This register must not be modified from the read value 001h RESERVED This register must not be modified from the read value 002h...
  • Page 24 8A3xxxx Family Programming Guide Table 11: GENERAL_STATUS Register Index Register Module Base Address: C014h Offset (Hex) Individual Register Name Register Description 023h GENERAL_STATUS.OTP_CONFIG_STATUS OTP soft CSR configuration status. 024h GENERAL_STATUS.OTP_CSR_CONFIG_STA OTP hard CSR configuration status. 025h RESERVED This register must not be modified from the read value 026h GENERAL_STATUS.EEPROM_CONFIG_STAT EEPROM soft CSR configuration status.
  • Page 25 8A3xxxx Family Programming Guide GENERAL_STATUS.OTP_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description OTP_STATUS[31:0] Current status of OTP. 0x000000 = no status 0x100000 = success 0x100001 = corrupted header 0x100002 = address out of range 0x100003 = corrupted section 0x100004 = invalid cluster index 0x100005 = redundant cluster not available 0x100006 = redundant cluster invalid index...
  • Page 26 8A3xxxx Family Programming Guide GENERAL_STATUS.EEPROM_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description EEPROM_STATUS[15:0] Current status of EEPROM. 0x0000 = no status 0x8000 = ok 0x8001 = unknown command 0x8002 = wrong size 0x8003 = out of range 0x8004 = read failed 0x8005 = write failed 0x8006 = verification failed...
  • Page 27 8A3xxxx Family Programming Guide GENERAL_STATUS.HOTFIX_REL Hotfix release number. e.g.. 1.2.Z Table 16: GENERAL_STATUS.HOTFIX_REL Bit Field Locations and Descriptions Offset GENERAL_STATUS.HOTFIX_REL Bit Field Locations Address (Hex) 012h HOTFIX[7:0] GENERAL_STATUS.HOTFIX_REL Bit Field Descriptions Bit Field Name Field Type Default Value Description HOTFIX[7:0] Hotfix release number.
  • Page 28 8A3xxxx Family Programming Guide GENERAL_STATUS.PRODUCT_ID Bit Field Descriptions Bit Field Name Field Type Default Value Description PRODUCT_ID[15:0] 16-bit Product ID code for this specific device, please refer to the Programming Guide Addendum for the specific device for expected value here. GENERAL_STATUS.TEMPERATURE 2s complement signed 16-bit numerical value in degrees Celsius.
  • Page 29 8A3xxxx Family Programming Guide GENERAL_STATUS.OTP_CONFIG_STATUS Status of soft CSR configuration loaded from OTP. Table 21: GENERAL_STATUS.OTP_CONFIG_STATUS Bit Field Locations and Descriptions Offset GENERAL_STATUS.OTP_CONFIG_STATUS Bit Field Locations Address (Hex) 023h OTP_SCSR_CONFIG_STATUS[7:0] GENERAL_STATUS.OTP_CONFIG_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description OTP_SCSR_CONFIG_ST Status code.
  • Page 30 8A3xxxx Family Programming Guide GENERAL_STATUS.EEPROM_CONFIG_STATUS Status of configuration loaded from EEPROM. Table 23: GENERAL_STATUS.EEPROM_CONFIG_STATUS Bit Field Locations and Descriptions Offset GENERAL_STATUS.EEPROM_CONFIG_STATUS Bit Field Locations Address (Hex) 026h EEPROM_CONFIG_STATUS[7:0] GENERAL_STATUS.EEPROM_CONFIG_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description EEPROM_CONFIG_STAT Status code.
  • Page 31 8A3xxxx Family Programming Guide Table 24: STATUS Register Index Register Module Base Address: C03Ch Offset (Hex) Individual Register Name Register Description 00Ch STATUS.IN4_MON_STATUS Input 4 reference monitor status. 00Dh STATUS.IN5_MON_STATUS Input 5 reference monitor status. 00Eh STATUS.IN6_MON_STATUS Input 6 reference monitor status. 00Fh STATUS.IN7_MON_STATUS Input 7 reference monitor status.
  • Page 32 8A3xxxx Family Programming Guide Table 24: STATUS Register Index Register Module Base Address: C03Ch Offset (Hex) Individual Register Name Register Description 04Ch STATUS.DPLL1_FILTER_STATUS DPLL 1 loop filter status. 054h STATUS.DPLL2_FILTER_STATUS DPLL 2 loop filter status. 05Ch STATUS.DPLL3_FILTER_STATUS DPLL 3 loop filter status. 064h STATUS.DPLL4_FILTER_STATUS DPLL 4 loop filter status.
  • Page 33 8A3xxxx Family Programming Guide Table 24: STATUS Register Index Register Module Base Address: C03Ch Offset (Hex) Individual Register Name Register Description 0BAh RESERVED This register must not be modified from the read value 0BBh RESERVED This register must not be modified from the read value 0C4h STATUS.OUTPUT_TDC1_MEASUREMENT Output TDC 1 measurement status.
  • Page 34 8A3xxxx Family Programming Guide Table 24: STATUS Register Index Register Module Base Address: C03Ch Offset (Hex) Individual Register Name Register Description 109h RESERVED This register must not be modified from the read value 10Ah RESERVED This register must not be modified from the read value 10Bh RESERVED This register must not be modified from the read value...
  • Page 35 8A3xxxx Family Programming Guide STATUS.I2CM_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value I2CM_SPEED[3:2] I2C Master speed. Indicates the I2C speed. 0 = 100 KHz 1 = 400 KHz 2 = 1 MHz I2CM_PORT_SEL[1:0] I2C Master port pin selection.
  • Page 36 8A3xxxx Family Programming Guide STATUS.SER0_SPI_STATUS Status of serial interface 0 SPI. Table 27: STATUS.SER0_SPI_STATUS Bit Field Locations and Descriptions Offset STATUS.SER0_SPI_STATUS Bit Field Locations Address (Hex) 003h RESERVED[7:5] SPI_SDO_D SPI_CLOCK SPI_DUPLE RESERVED[1:0] ELAY[4] _SELECTIO X_MODE[2] N[3] STATUS.SER0_SPI_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 37 8A3xxxx Family Programming Guide STATUS.SER1_STATUS Status of serial interface 1. Table 29: STATUS.SER1_STATUS Bit Field Locations and Descriptions Offset STATUS.SER1_STATUS Bit Field Locations Address (Hex) 005h RESERVED[7:3] ADDRESS_S MODE[1:0] IZE[2] STATUS.SER1_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 38 8A3xxxx Family Programming Guide STATUS.SER1_SPI_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description SPI_SDO_DELAY[4] SPI delay SDO driving edge. 0 = driving edge used for SDO 1 = SDO driving edge delayed half-cycle of SCLK SPI_CLOCK_SELECTION[ SPI Clock Selection for SDI sampling. Indicates if the SPI clock selection is on a rising or falling edge.
  • Page 39 8A3xxxx Family Programming Guide STATUS.IN0_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN0_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 0. 0 = no change 1 = live status changed IN0_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 40 8A3xxxx Family Programming Guide STATUS.IN1_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN1_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 1. 0 = no change 1 = live status changed IN1_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 41 8A3xxxx Family Programming Guide STATUS.IN2_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN2_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 2. 0 = no change 1 = live status changed IN2_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 42 8A3xxxx Family Programming Guide STATUS.IN3_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN3_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 3. 0 = no change 1 = live status changed IN3_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 43 8A3xxxx Family Programming Guide STATUS.IN4_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN4_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 4. 0 = no change 1 = live status changed IN4_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 44 8A3xxxx Family Programming Guide STATUS.IN5_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN5_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 5. 0 = no change 1 = live status changed IN5_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 45 8A3xxxx Family Programming Guide STATUS.IN6_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN6_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 6. 0 = no change 1 = live status changed IN6_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 46 8A3xxxx Family Programming Guide STATUS.IN7_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN7_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 7. 0 = no change 1 = live status changed IN7_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 47 8A3xxxx Family Programming Guide STATUS.IN8_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN8_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 8. 0 = no change 1 = live status changed IN8_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 48 8A3xxxx Family Programming Guide STATUS.IN9_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN9_FREQ_OFFS_LIM_ST Frequency offset limit sticky bit. ICKY[6] Indicates that frequency offset limit was exceeded for input 9. 0 = no change 1 = live status changed IN9_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 49 8A3xxxx Family Programming Guide STATUS.IN10_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN10_FREQ_OFFS_LIM_S Frequency offset limit sticky bit. TICKY[6] Indicates that frequency offset limit was exceeded for input 10. 0 = no change 1 = live status changed IN10_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 50 8A3xxxx Family Programming Guide STATUS.IN11_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN11_FREQ_OFFS_LIM_S Frequency offset limit sticky bit. TICKY[6] Indicates that frequency offset limit was exceeded for input 11. 0 = no change 1 = live status changed IN11_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 51 8A3xxxx Family Programming Guide STATUS.IN12_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN12_FREQ_OFFS_LIM_S Frequency offset limit sticky bit. TICKY[6] Indicates that frequency offset limit was exceeded for input 12. 0 = no change 1 = live status changed IN12_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 52 8A3xxxx Family Programming Guide STATUS.IN13_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN13_FREQ_OFFS_LIM_S Frequency offset limit sticky bit. TICKY[6] Indicates that frequency offset limit was exceeded for input 13. 0 = no change 1 = live status changed IN13_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 53 8A3xxxx Family Programming Guide STATUS.IN14_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN14_FREQ_OFFS_LIM_S Frequency offset limit sticky bit. TICKY[6] Indicates that frequency offset limit was exceeded for input 14. 0 = no change 1 = live status changed IN14_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 54 8A3xxxx Family Programming Guide STATUS.IN15_MON_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description IN15_FREQ_OFFS_LIM_S Frequency offset limit sticky bit. TICKY[6] Indicates that frequency offset limit was exceeded for input 15. 0 = no change 1 = live status changed IN15_NO_ACTIVITY_STIC No activity sticky bit.
  • Page 55 8A3xxxx Family Programming Guide STATUS.DPLL0_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL0_HOLDOVER_STAT Holdover state change sticky bit. E_CHANGE_STICKY[5] Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state DPLL0_LOCK_STATE_CH...
  • Page 56 8A3xxxx Family Programming Guide STATUS.DPLL1_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL1_LOCK_STATE_CH Lock state change sticky bit. ANGE_STICKY[4] Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state DPLL1_STATE[3:0] Current state of DPLL1.
  • Page 57 8A3xxxx Family Programming Guide STATUS.DPLL3_STATUS DPLL 3 status. Table 51: STATUS.DPLL3_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL3_STATUS Bit Field Locations Address (Hex) 01Bh RESERVED[7:6] DPLL3_HOL DPLL3_LOC DPLL3_STATE[3:0] DOVER_STA K_STATE_C TE_CHANG HANGE_STI E_STICKY[5] CKY[4] STATUS.DPLL3_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED...
  • Page 58 8A3xxxx Family Programming Guide STATUS.DPLL4_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL4_HOLDOVER_STAT Holdover state change sticky bit. E_CHANGE_STICKY[5] Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state DPLL4_LOCK_STATE_CH...
  • Page 59 8A3xxxx Family Programming Guide STATUS.DPLL5_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL5_LOCK_STATE_CH Lock state change sticky bit. ANGE_STICKY[4] Indicates whether any transition to or from Locked state occurred. 0 = no transition to or from Locked state 1 = transition to or from Locked state DPLL5_STATE[3:0] Current state of DPLL5.
  • Page 60 8A3xxxx Family Programming Guide STATUS.DPLL7_STATUS DPLL 7 status. Table 55: STATUS.DPLL7_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL7_STATUS Bit Field Locations Address (Hex) 01Fh RESERVED[7:6] DPLL7_HOL DPLL7_LOC DPLL7_STATE[3:0] DOVER_STA K_STATE_C TE_CHANG HANGE_STI E_STICKY[5] CKY[4] STATUS.DPLL7_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED...
  • Page 61 8A3xxxx Family Programming Guide STATUS.DPLL_SYS_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL_SYS_HOLDOVER_ Holdover state change sticky bit. STATE_CHANGE_STICKY Indicates whether any transition to or from Holdover state occurred. 0 = no transition to or from Holdover state 1 = transition to or from Holdover state DPLL_SYS_LOCK_STATE...
  • Page 62 8A3xxxx Family Programming Guide STATUS.DPLL0_REF_STAT Indicates which reference is currently selected for tracking. Table 58: STATUS.DPLL0_REF_STAT Bit Field Locations and Descriptions Offset STATUS.DPLL0_REF_STAT Bit Field Locations Address (Hex) 022h RESERVED[7:5] DPLL0_INPUT[4:0] STATUS.DPLL0_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 63 8A3xxxx Family Programming Guide STATUS.DPLL1_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL1_INPUT[4:0] Current reference input for DPLL 1. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 64 8A3xxxx Family Programming Guide STATUS.DPLL2_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL2_INPUT[4:0] Current reference input for DPLL 2. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 65 8A3xxxx Family Programming Guide STATUS.DPLL3_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL3_INPUT[4:0] Current reference input for DPLL 3. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 66 8A3xxxx Family Programming Guide STATUS.DPLL4_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL4_INPUT[4:0] Current reference input for DPLL 4. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 67 8A3xxxx Family Programming Guide STATUS.DPLL5_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL5_INPUT[4:0] Current reference input for DPLL 5. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 68 8A3xxxx Family Programming Guide STATUS.DPLL6_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL6_INPUT[4:0] Current reference input for DPLL 6. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 69 8A3xxxx Family Programming Guide STATUS.DPLL7_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL7_INPUT[4:0] Current reference input for DPLL 7. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 70 8A3xxxx Family Programming Guide STATUS.DPLL_SYS_REF_STAT Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL_SYS_INPUT[4:0] Current reference input for system DPLL. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3 0x04 = CLK4...
  • Page 71 8A3xxxx Family Programming Guide STATUS.DPLL1_FILTER_STATUS DPLL 1 loop filter status. Table 68: STATUS.DPLL1_FILTER_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL1_FILTER_STATUS Bit Field Locations Address (Hex) 04Ch FILTER_STATUS[7:0] 04Dh FILTER_STATUS[15:8] 04Eh FILTER_STATUS[23:16] 04Fh FILTER_STATUS[31:24] 050h FILTER_STATUS[39:32] 051h FILTER_STATUS[47:40] STATUS.DPLL1_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 72 8A3xxxx Family Programming Guide STATUS.DPLL3_FILTER_STATUS DPLL 3 loop filter status. Table 70: STATUS.DPLL3_FILTER_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL3_FILTER_STATUS Bit Field Locations Address (Hex) 05Ch FILTER_STATUS[7:0] 05Dh FILTER_STATUS[15:8] 05Eh FILTER_STATUS[23:16] 05Fh FILTER_STATUS[31:24] 060h FILTER_STATUS[39:32] 061h FILTER_STATUS[47:40] STATUS.DPLL3_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 73 8A3xxxx Family Programming Guide STATUS.DPLL5_FILTER_STATUS DPLL 5 loop filter status. Table 72: STATUS.DPLL5_FILTER_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL5_FILTER_STATUS Bit Field Locations Address (Hex) 06Ch FILTER_STATUS[7:0] 06Dh FILTER_STATUS[15:8] 06Eh FILTER_STATUS[23:16] 06Fh FILTER_STATUS[31:24] 070h FILTER_STATUS[39:32] 071h FILTER_STATUS[47:40] STATUS.DPLL5_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 74 8A3xxxx Family Programming Guide STATUS.DPLL7_FILTER_STATUS DPLL 7 loop filter status. Table 74: STATUS.DPLL7_FILTER_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL7_FILTER_STATUS Bit Field Locations Address (Hex) 07Ch FILTER_STATUS[7:0] 07Dh FILTER_STATUS[15:8] 07Eh FILTER_STATUS[23:16] 07Fh FILTER_STATUS[31:24] 080h FILTER_STATUS[39:32] 081h FILTER_STATUS[47:40] STATUS.DPLL7_FILTER_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 75 8A3xxxx Family Programming Guide STATUS.USER_GPIO0_TO_7_STATUS GPIO 0 - 7 level status. Table 76: STATUS.USER_GPIO0_TO_7_STATUS Bit Field Locations and Descriptions Offset STATUS.USER_GPIO0_TO_7_STATUS Bit Field Locations Address (Hex) 08Ah GPIO7_LEV GPIO6_LEV GPIO5_LEV GPIO4_LEV GPIO3_LEV GPIO2_LEV GPIO1_LEV GPIO0_LEV EL[7] EL[6] EL[5] EL[4] EL[3] EL[2] EL[1] EL[0]...
  • Page 76 8A3xxxx Family Programming Guide STATUS.USER_GPIO8_TO_15_STATUS GPIO 8 - 15 level status. Table 77: STATUS.USER_GPIO8_TO_15_STATUS Bit Field Locations and Descriptions Offset STATUS.USER_GPIO8_TO_15_STATUS Bit Field Locations Address (Hex) 08Bh GPIO15_LEV GPIO14_LEV GPIO13_LEV GPIO12_LEV GPIO11_LEV GPIO10_LEV GPIO9_LEV GPIO8_LEV EL[7] EL[6] EL[5] EL[4] EL[3] EL[2] EL[1] EL[0]...
  • Page 77 8A3xxxx Family Programming Guide STATUS.IN0_MON_FREQ_STATUS Input 0 reference monitor frequency status and unit. Table 78: STATUS.IN0_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN0_MON_FREQ_STATUS Bit Field Locations Address (Hex) 08Ch FFO[7:0] 08Dh FFO_UNIT[15:14] FFO[13:8] STATUS.IN0_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 78 8A3xxxx Family Programming Guide STATUS.IN2_MON_FREQ_STATUS Input 2 reference monitor frequency status and unit. Table 80: STATUS.IN2_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN2_MON_FREQ_STATUS Bit Field Locations Address (Hex) 090h FFO[7:0] 091h FFO_UNIT[15:14] FFO[13:8] STATUS.IN2_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 79 8A3xxxx Family Programming Guide STATUS.IN4_MON_FREQ_STATUS Input 4 reference monitor frequency status and unit. Table 82: STATUS.IN4_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN4_MON_FREQ_STATUS Bit Field Locations Address (Hex) 094h FFO[7:0] 095h FFO_UNIT[15:14] FFO[13:8] STATUS.IN4_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 80 8A3xxxx Family Programming Guide STATUS.IN6_MON_FREQ_STATUS Input 6 reference monitor frequency status and unit. Table 84: STATUS.IN6_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN6_MON_FREQ_STATUS Bit Field Locations Address (Hex) 098h FFO[7:0] 099h FFO_UNIT[15:14] FFO[13:8] STATUS.IN6_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 81 8A3xxxx Family Programming Guide STATUS.IN8_MON_FREQ_STATUS Input 8 reference monitor frequency status and unit. Table 86: STATUS.IN8_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN8_MON_FREQ_STATUS Bit Field Locations Address (Hex) 09Ch FFO[7:0] 09Dh FFO_UNIT[15:14] FFO[13:8] STATUS.IN8_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 82 8A3xxxx Family Programming Guide STATUS.IN10_MON_FREQ_STATUS Input 10 reference monitor frequency status and unit. Table 88: STATUS.IN10_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN10_MON_FREQ_STATUS Bit Field Locations Address (Hex) 0A0h FFO[7:0] 0A1h FFO_UNIT[15:14] FFO[13:8] STATUS.IN10_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 83 8A3xxxx Family Programming Guide STATUS.IN12_MON_FREQ_STATUS Input 12 reference monitor frequency status and unit. Table 90: STATUS.IN12_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN12_MON_FREQ_STATUS Bit Field Locations Address (Hex) 0A4h FFO[7:0] 0A5h FFO_UNIT[15:14] FFO[13:8] STATUS.IN12_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 84 8A3xxxx Family Programming Guide STATUS.IN14_MON_FREQ_STATUS Input 14 reference monitor frequency status and unit. Table 92: STATUS.IN14_MON_FREQ_STATUS Bit Field Locations and Descriptions Offset STATUS.IN14_MON_FREQ_STATUS Bit Field Locations Address (Hex) 0A8h FFO[7:0] 0A9h FFO_UNIT[15:14] FFO[13:8] STATUS.IN14_MON_FREQ_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[15:14]...
  • Page 85 8A3xxxx Family Programming Guide STATUS.OUTPUT_TDC_CFG_STATUS Indicates when the output TDC is ready for use. Table 94: STATUS.OUTPUT_TDC_CFG_STATUS Bit Field Locations and Descriptions Offset STATUS.OUTPUT_TDC_CFG_STATUS Bit Field Locations Address (Hex) 0ACh RESERVED[7:2] STATE[1:0] STATUS.OUTPUT_TDC_CFG_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 86 8A3xxxx Family Programming Guide STATUS.OUTPUT_TDC0_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value STATUS[3:0] Status code. When output TDC is not enabled, this shows 'Disabled'. When OUTPUT_TDC_CTRL_4.GO is set and the configuration is valid, this transitions to 'In progress'.
  • Page 87 8A3xxxx Family Programming Guide STATUS.OUTPUT_TDC1_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value STATUS[3:0] Status code. When output TDC is not enabled, this shows 'Disabled'. When OUTPUT_TDC_CTRL_4.GO is set and the configuration is valid, this transitions to 'In progress'.
  • Page 88 8A3xxxx Family Programming Guide STATUS.OUTPUT_TDC2_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value STATUS[3:0] Status code. When output TDC is not enabled, this shows 'Disabled'. When OUTPUT_TDC_CTRL_4.GO is set and the configuration is valid, this transitions to 'In progress'.
  • Page 89 8A3xxxx Family Programming Guide STATUS.OUTPUT_TDC3_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value STATUS[3:0] Status code. When output TDC is not enabled, this shows 'Disabled'. When OUTPUT_TDC_CTRL_4.GO is set and the configuration is valid, this transitions to 'In progress'.
  • Page 90 8A3xxxx Family Programming Guide STATUS.OUTPUT_TDC1_MEASUREMENT Indicates output TDC 1 measurement. Table 100: STATUS.OUTPUT_TDC1_MEASUREMENT Bit Field Locations and Descriptions Offset STATUS.OUTPUT_TDC1_MEASUREMENT Bit Field Locations Address (Hex) 0C4h PHASE[7:0] 0C5h PHASE[15:8] 0C6h PHASE[23:16] 0C7h PHASE[31:24] 0C8h PHASE[39:32] 0C9h PHASE[47:40] STATUS.OUTPUT_TDC1_MEASUREMENT Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 91 8A3xxxx Family Programming Guide STATUS.OUTPUT_TDC2_MEASUREMENT Bit Field Descriptions Bit Field Name Field Type Default Value Description PHASE[47:0] Output TDC measurement. Signed 48-bit integer in picoseconds. Measurement = sum of samples / number of samples A sample is collected every 100us. Positive value indicates the target edge leads the source edge.
  • Page 92 8A3xxxx Family Programming Guide STATUS.DPLL0_PHASE_STATUS Phase offset at output of decimator. Table 103: STATUS.DPLL0_PHASE_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL0_PHASE_STATUS Bit Field Locations Address (Hex) 0DCh DPLL0_PHASE_STATUS[7:0] 0DDh DPLL0_PHASE_STATUS[15:8] 0DEh DPLL0_PHASE_STATUS[23:16] 0DFh DPLL0_PHASE_STATUS[31:24] 0E0h RESERVED[39:36] DPLL0_PHASE_STATUS[35:32] STATUS.DPLL0_PHASE_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 93 8A3xxxx Family Programming Guide STATUS.DPLL2_PHASE_STATUS Phase offset at output of decimator. Table 105: STATUS.DPLL2_PHASE_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL2_PHASE_STATUS Bit Field Locations Address (Hex) 0ECh DPLL2_PHASE_STATUS[7:0] 0EDh DPLL2_PHASE_STATUS[15:8] 0EEh DPLL2_PHASE_STATUS[23:16] 0EFh DPLL2_PHASE_STATUS[31:24] 0F0h RESERVED[39:36] DPLL2_PHASE_STATUS[35:32] STATUS.DPLL2_PHASE_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 94 8A3xxxx Family Programming Guide STATUS.DPLL4_PHASE_STATUS Phase offset at output of decimator. Table 107: STATUS.DPLL4_PHASE_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL4_PHASE_STATUS Bit Field Locations Address (Hex) 0FCh DPLL4_PHASE_STATUS[7:0] 0FDh DPLL4_PHASE_STATUS[15:8] 0FEh DPLL4_PHASE_STATUS[23:16] 0FFh DPLL4_PHASE_STATUS[31:24] 100h RESERVED[39:36] DPLL4_PHASE_STATUS[35:32] STATUS.DPLL4_PHASE_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 95 8A3xxxx Family Programming Guide STATUS.DPLL6_PHASE_STATUS Phase offset at output of decimator. Table 109: STATUS.DPLL6_PHASE_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL6_PHASE_STATUS Bit Field Locations Address (Hex) 10Ch DPLL6_PHASE_STATUS[7:0] 10Dh DPLL6_PHASE_STATUS[15:8] 10Eh DPLL6_PHASE_STATUS[23:16] 10Fh DPLL6_PHASE_STATUS[31:24] 110h RESERVED[39:36] DPLL6_PHASE_STATUS[35:32] STATUS.DPLL6_PHASE_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 96 8A3xxxx Family Programming Guide STATUS.DPLL0_PHASE_PULL_IN_STATUS DPLL0 phase pull-in status Table 111: STATUS.DPLL0_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL0_PHASE_PULL_IN_STATUS Bit Field Locations Address (Hex) 11Ch REMAINING_TIME[7:0] STATUS.DPLL0_PHASE_PULL_IN_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description REMAINING_TIME[7:0] Unsigned 8-bit phase pull-in time to finish in seconds. If the value of this field <...
  • Page 97 8A3xxxx Family Programming Guide STATUS.DPLL2_PHASE_PULL_IN_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description REMAINING_TIME[7:0] Unsigned 8-bit phase pull-in time to finish in seconds. If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds.
  • Page 98 8A3xxxx Family Programming Guide STATUS.DPLL5_PHASE_PULL_IN_STATUS DPLL5 phase pull-in status Table 116: STATUS.DPLL5_PHASE_PULL_IN_STATUS Bit Field Locations and Descriptions Offset STATUS.DPLL5_PHASE_PULL_IN_STATUS Bit Field Locations Address (Hex) 121h REMAINING_TIME[7:0] STATUS.DPLL5_PHASE_PULL_IN_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description REMAINING_TIME[7:0] Unsigned 8-bit phase pull-in time to finish in seconds. If the value of this field <...
  • Page 99 8A3xxxx Family Programming Guide STATUS.DPLL7_PHASE_PULL_IN_STATUS Bit Field Descriptions Bit Field Name Field Type Default Value Description REMAINING_TIME[7:0] Unsigned 8-bit phase pull-in time to finish in seconds. If the value of this field < 255, the actual remaining time is between (remaining_time) and (remaining_time + 1) seconds.
  • Page 100 8A3xxxx Family Programming Guide GPIO_USER_CONTROL.GPIO0_TO_7_OUT Bit Field Descriptions Bit Field Name Field Type Default Value Description GPIO4_DRIVE_LEVEL[4] GPIO pin 4 drive level. Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high GPIO3_DRIVE_LEVEL[3] GPIO pin 3 drive level.
  • Page 101 8A3xxxx Family Programming Guide GPIO_USER_CONTROL.GPIO8_TO_15_OUT Bit Field Descriptions Bit Field Name Field Type Default Value Description GPIO15_DRIVE_LEVEL[7] GPIO pin 15 drive level. Valid only if GPIO_FUNCTION is disabled and 'gpio_control_dir' is output. 0 = drive low 1 = drive high GPIO14_DRIVE_LEVEL[6] GPIO pin 14 drive level.
  • Page 102 8A3xxxx Family Programming Guide Table 122: STICKY_STATUS_CLEAR Register Index Register Module Base Address: C164h Offset (Hex) Individual Register Name Register Description 000h STICKY_STATUS_CLEAR.IN0_TO_7_MON_S Clear sticky reference monitor status. TICKY_STATUS_CLEAR 001h STICKY_STATUS_CLEAR.IN8_TO_15_MON_S Clear sticky reference monitor status. TICKY_STATUS_CLEAR 002h STICKY_STATUS_CLEAR.DPLL_STICKY_STA Clear sticky DPLL status. TUS_CLEAR 003h STICKY_STATUS_CLEAR.DPLL_SYS_STICKY...
  • Page 103 8A3xxxx Family Programming Guide STICKY_STATUS_CLEAR.IN0_TO_7_MON_STICKY_STATUS_CLEAR Bit Field Descriptions Bit Field Name Field Type Default Value Description IN2_MON_STICKY_CLEA RW1C Write 1 to clear the sticky bits of input 2. R[2] IN1_MON_STICKY_CLEA RW1C Write 1 to clear the sticky bits of input 1. R[1] IN0_MON_STICKY_CLEA RW1C...
  • Page 104 8A3xxxx Family Programming Guide STICKY_STATUS_CLEAR.DPLL_STICKY_STATUS_CLEAR Clear sticky state change bits for a particular DPLL. Table 125: STICKY_STATUS_CLEAR.DPLL_STICKY_STATUS_CLEAR Bit Field Locations and Descriptions Offset STICKY_STATUS_CLEAR.DPLL_STICKY_STATUS_CLEAR Bit Field Locations Address (Hex) 002h DPLL7_STIC DPLL6_STIC DPLL5_STIC DPLL4_STIC DPLL3_STIC DPLL2_STIC DPLL1_STIC DPLL0_STIC KY_CLEAR[7 KY_CLEAR[6 KY_CLEAR[5 KY_CLEAR[4 KY_CLEAR[3...
  • Page 105 8A3xxxx Family Programming Guide STICKY_STATUS_CLEAR.DPLL_SYS_STICKY_STATUS_CLEAR Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL_SYS_STICKY_CLE RW1C Write 1 to clear the sticky bits of system DPLL. AR[0] STICKY_STATUS_CLEAR.SYS_APLL_STICKY_STATUS_CLEAR Clear sticky loss-of-lock bit for system APLL.
  • Page 106 8A3xxxx Family Programming Guide Module: GPIO_TOD_NOTIFICATION_CLEAR TRIGGER: Writing to this byte triggers a read and activation in hardware of all the bytes of the SYS_TOD_NOTIFICATION_CLEAR module. Table 129: GPIO_TOD_NOTIFICATION_CLEAR Register Index Register Module Base Address: C16Ch Offset (Hex) Individual Register Name Register Description 000h GPIO_TOD_NOTIFICATION_CLEAR.GPIO0_T...

  • Page 107: Table Of Contents

    8A3xxxx Family Programming Guide GPIO_TOD_NOTIFICATION_CLEAR.GPIO8_TO_15_CLEAR Bit Field Descriptions Bit Field Name Field Type Default Value Description GPIO15_CLEAR[7] RW1C Write 1 to clear GPIO15 assertion. GPIO14_CLEAR[6] RW1C Write 1 to clear GPIO14 assertion. GPIO13_CLEAR[5] RW1C Write 1 to clear GPIO13 assertion. GPIO12_CLEAR[4] RW1C Write 1 to clear GPIO12 assertion.

  • Page 108: Offset

    8A3xxxx Family Programming Guide ALERT_CFG.IN1_0_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 0 and 1. Table 133: ALERT_CFG.IN1_0_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN1_0_MON_ALERT_MASK Bit Field Locations Address (Hex) 000h RESERVED[ IN1_FREQ_ IN1_NO_AC IN1_LOS_M RESERVED[...

  • Page 109: Alert_Cfg.in3_2_Mon_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.IN3_2_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 2 and 3. Table 134: ALERT_CFG.IN3_2_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN3_2_MON_ALERT_MASK Bit Field Locations Address (Hex) 001h RESERVED[ IN3_FREQ_ IN3_NO_AC IN3_LOS_M RESERVED[...

  • Page 110: Alert_Cfg.in5_4_Mon_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.IN5_4_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 4 and 5. Table 135: ALERT_CFG.IN5_4_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN5_4_MON_ALERT_MASK Bit Field Locations Address (Hex) 002h RESERVED[ IN5_FREQ_ IN5_NO_AC IN5_LOS_M RESERVED[...

  • Page 111: Alert_Cfg.in7_6_Mon_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.IN7_6_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 7 and 6. Table 136: ALERT_CFG.IN7_6_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN7_6_MON_ALERT_MASK Bit Field Locations Address (Hex) 003h RESERVED[ IN7_FREQ_ IN7_NO_AC IN7_LOS_M RESERVED[...

  • Page 112: Alert_Cfg.in9_8_Mon_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.IN9_8_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 8 and 9. Table 137: ALERT_CFG.IN9_8_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN9_8_MON_ALERT_MASK Bit Field Locations Address (Hex) 004h RESERVED[ IN9_FREQ_ IN9_NO_AC IN9_LOS_M RESERVED[...

  • Page 113: Alert_Cfg.in11_10_Mon_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.IN11_10_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 10 and 11. Table 138: ALERT_CFG.IN11_10_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN11_10_MON_ALERT_MASK Bit Field Locations Address (Hex) 005h RESERVED[ IN11_FREQ_ IN11_NO_AC IN11_LOS_M RESERVED[...

  • Page 114: Alert_Cfg.in13_12_Mon_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.IN13_12_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 12 and 13. Table 139: ALERT_CFG.IN13_12_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN13_12_MON_ALERT_MASK Bit Field Locations Address (Hex) 006h RESERVED[ IN13_FREQ_ IN13_NO_A IN13_LOS_M RESERVED[...

  • Page 115: Alert_Cfg.in15_14_Mon_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.IN15_14_MON_ALERT_MASK GPIO alert enable masks (frequency offset, no activity, loss of signal) for reference monitors 14 and 15. Table 140: ALERT_CFG.IN15_14_MON_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.IN15_14_MON_ALERT_MASK Bit Field Locations Address (Hex) 007h RESERVED[ IN15_FREQ_ IN15_NO_A IN15_LOS_M RESERVED[...
  • Page 116 8A3xxxx Family Programming Guide ALERT_CFG.DPLL3_2_1_0_ALERT_MASK GPIO alert enable masks (holdover, lock) for DPLL 0, 1, 2 and 3. Table 141: ALERT_CFG.DPLL3_2_1_0_ALERT_MASK Bit Field Locations and Descriptions Offset ALERT_CFG.DPLL3_2_1_0_ALERT_MASK Bit Field Locations Address (Hex) 008h DPLL3_HOL DPLL3_LOC DPLL2_HOL DPLL2_LOC DPLL1_HOL DPLL1_LOC DPLL0_HOL DPLL0_LOC DOVER_MA...
  • Page 117 8A3xxxx Family Programming Guide ALERT_CFG.DPLL3_2_1_0_ALERT_MASK Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL0_HOLDOVER_MAS DPLL 0 holdover state transition event enable mask. K[1] If enabled, GPIO alert becomes active when dpll0_holdover_state_change_sticky bit is set. 0 = disabled 1 = enabled DPLL0_LOCK_MASK[0] DPLL 0 lock state transition event enable mask.

  • Page 118: Alert_Cfg.sys_Alert_Mask

    8A3xxxx Family Programming Guide ALERT_CFG.DPLL7_6_5_4_ALERT_MASK Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL6_LOCK_MASK[4] DPLL 6 lock state transition event enable mask. If enabled, GPIO alert becomes active when dpll6_lock_state_change_sticky bit is set. 0 = disabled 1 = enabled DPLL5_HOLDOVER_MAS DPLL 5 holdover state transition event enable mask.
  • Page 119 8A3xxxx Family Programming Guide ALERT_CFG.SYS_ALERT_MASK Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value SYS_APLL_LOSS_LOCK_ System APLL loss lock event enable mask. MASK[2] If enabled, GPIO alert becomes active when sys_apll_loss_lock_sticky bit is set. 0 = disabled 1 = enabled DPLL_SYS_HOLDOVER_...
  • Page 120 8A3xxxx Family Programming Guide Table 145: SYS_DPLL_XO.XO_FREQ Bit Field Locations and Descriptions Offset SYS_DPLL_XO.XO_FREQ Bit Field Locations Address (Hex) 004h M[39:32] 005h M[47:40] 006h N[7:0] 007h N[15:8] SYS_DPLL_XO.XO_FREQ Bit Field Descriptions Bit Field Name Field Type Default Value Description N[15:0] XO_DPLL frequency N.
  • Page 121 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_CP_SS_CURRENT_1 Set the charge pump source switching currents and enable for config. Table 147: SYS_APLL.SYS_APLL_CP_SS_CURRENT_1 Bit Field Locations and Descriptions Offset SYS_APLL.SYS_APLL_CP_SS_CURRENT_1 Bit Field Locations Address (Hex) 000h GLOBAL_EN RESERVED[ CP_1_SS_CURRENT[5:3] CP_2_SS_CURRENT[2:0] ABLE[7] SYS_APLL.SYS_APLL_CP_SS_CURRENT_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 122 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_CP_SS_CURRENT_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value CP_3_SS_CURRENT[5:3] 0x0 = 125uA, 0x3 = 500uA, 0x7 = 1000uA. Reference current for Charge Pump #3. 125uA steps. For use in 3.3V VDDA operation.
  • Page 123 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_CFG_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description PFD_RESET_CS[1] Reset to 2.5V current steering PFD. Reset must be high for 3.3V VDDA operation, low for 2.5V VDDA operation. PFD_RESET_SS_1[0] Reset to 3.3V source switching PFD #1. Reset must be high for 2.5V VDDA operation, low for 3.3V VDDA operation.
  • Page 124 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_VREG_CTRL VREG control register. Table 151: SYS_APLL.SYS_APLL_VREG_CTRL Bit Field Locations and Descriptions Offset SYS_APLL.SYS_APLL_VREG_CTRL Bit Field Locations Address (Hex) 004h RESERVED[7:1] VREG_VCAL _0[0] SYS_APLL.SYS_APLL_VREG_CTRL Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value VREG_VCAL_0[0] VREG volt calibration control register bit 0.
  • Page 125 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_CP_CTRL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description CP_2_SS_ENABLE[5] Enable source switching charge pump #2. Must be low for 2.5V VDDA. 0 = disabled 1 = enabled. CP_1_SS_ENABLE[4] Enable source switching charge pump #1. Must be low for 2.5V VDDA.
  • Page 126 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_CP_CTRL_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description SYS_APLL_CP_4_SS_125 Enable source switching 125mA gain control for Charge Pump #4. U_ENABLE[7] For use in 3.3V VDDA operation 0 = disabled 1 = enabled. SYS_APLL_CP_3_SS_125 Enable source switching 125mA gain control for Charge Pump #3.
  • Page 127 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_CP_CTRL_2 Sets the charge pump and 500uA enables for control 2. Table 154: SYS_APLL.SYS_APLL_CP_CTRL_2 Bit Field Locations and Descriptions Offset SYS_APLL.SYS_APLL_CP_CTRL_2 Bit Field Locations Address (Hex) 007h SYS_APLL_ SYS_APLL_ SYS_APLL_ SYS_APLL_ SYS_APLL_ SYS_APLL_ SYS_APLL_ SYS_APLL_ CP_4_SS_O CP_3_SS_O CP_2_SS_O CP_1_SS_O...
  • Page 128 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_XTAL_FREQ Crystal (XTAL) Frequency in Hz M/N. Table 155: SYS_APLL.SYS_APLL_XTAL_FREQ Bit Field Locations and Descriptions Offset SYS_APLL.SYS_APLL_XTAL_FREQ Bit Field Locations Address (Hex) 008h M[7:0] 009h M[15:8] 00Ah M[23:16] 00Bh M[31:24] 00Ch M[39:32] 00Dh M[47:40] 00Eh N[7:0] 00Fh N[15:8] SYS_APLL.SYS_APLL_XTAL_FREQ Bit Field Descriptions...
  • Page 129 8A3xxxx Family Programming Guide SYS_APLL.SYS_APLL_CTRL Bit Field Descriptions Bit Field Name Field Type Default Value Description VCCA_SEL[15] VCCA selection. If SYS_APLL_CP_SS_CURRENT_1.GLOBAL_ENABLE is set to "0", this field selects 2.5V or 3.3V VDDA operation with default charge pump values. If SYS_APLL_CP_SS_CURRENT_1.GLOBAL_ENABLE is set to "1", this field will be ignored and the charge pump fields can be programmed to customized values.

  • Page 130: Offset

    8A3xxxx Family Programming Guide INPUT_0.IN_FREQ Input frequency in Hz is M / N. Table 158: INPUT_0.IN_FREQ Bit Field Locations and Descriptions Offset INPUT_0.IN_FREQ Bit Field Locations Address (Hex) 000h M[7:0] 001h M[15:8] 002h M[23:16] 003h M[31:24] 004h M[39:32] 005h M[47:40] 006h N[7:0] 007h...

  • Page 131: Input_0.In_Phase

    8A3xxxx Family Programming Guide INPUT_0.IN_DIV Bit Field Descriptions Bit Field Name Field Type Default Value Description IN_DIV[15:0] Divide IN_FREQ down to send to the DPLL. Unsigned 16-bit number. Maximum speed for the references sent to the DPLL is 200 MHz. 0 and 1 both indicate bypass.
  • Page 132 8A3xxxx Family Programming Guide INPUT_0.IN_SYNC Bit Field Descriptions Bit Field Name Field Type Default Value Description FRAME_SYNC_PULSE_E Enable or disable the frame pulse or sync pulse mode for this input. N[7] Mode selection is determined by frame_sync_mode in SCSR_DPLL_CTRL_2. 0 = disabled 1 = enabled FRAME_SYNC_RESAMPL Re-sample edge selection.
  • Page 133 8A3xxxx Family Programming Guide INPUT_0.IN_SYNC Bit Field Descriptions Bit Field Name Field Type Default Value Description FRAME_SYNC_RESAMPL Re-sample enable. E_EN[5] Enabling re-sample will have the frame/sync input signal being re-sampled by the input reference clock (refclk). It can help to re-align the frame/sync with respect to the refclk.

  • Page 134: Input_0.In_Mode

    8A3xxxx Family Programming Guide INPUT_0.IN_MODE Configure the electrical properties of this input and select the predefined DPLL loop filter configuration. TRIGGER: Writing to this byte triggers a read and activation in hardware of all the bytes of the INPUT module. Table 162: INPUT_0.IN_MODE Bit Field Locations and Descriptions Offset INPUT_0.IN_MODE Bit Field Locations...

  • Page 135: This Register Module Is Instantiated Multiple Times. This Is The Base Address Of The First Instantiation Of This Module. For Later Instantiations

    8A3xxxx Family Programming Guide INPUT_0.IN_MODE Bit Field Descriptions Bit Field Name Field Type Default Value Description IN_PNMODE[4] Select PMOS or NMOS differential mode. Only applicable in differential mode. 0 = NMOS 1 = PMOS IN_INVERSE[3] Invert input. 0 = normal 1 = inverse RESERVED This field must not be modified from the read value...
  • Page 136 8A3xxxx Family Programming Guide REF_MON_0.IN_MON_FREQ_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value VLD_INTERVAL[6:3] Frequency validation interval. Frequency validation interval in seconds. The long term reference monitor uses VLD_INTERVAL as the period to measure the frequency offset.
  • Page 137 8A3xxxx Family Programming Guide REF_MON_0.IN_MON_TRANS_THRESHOLD Unsigned 16-bit value in nanoseconds. Table 166: REF_MON_0.IN_MON_TRANS_THRESHOLD Bit Field Locations and Descriptions Offset REF_MON_0.IN_MON_TRANS_THRESHOLD Bit Field Locations Address (Hex) 002h IN_MON_TRANS_THRESHOLD[7:0] 003h IN_MON_TRANS_THRESHOLD[15:8] REF_MON_0.IN_MON_TRANS_THRESHOLD Bit Field Descriptions Bit Field Name Field Type Default Value Description IN_MON_TRANS_THRES Reference phase transient detection threshold in nanoseconds.
  • Page 138 8A3xxxx Family Programming Guide REF_MON_0.IN_MON_ACT_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value QUAL_TIMER[6:5] Reference activity qualification timer enumeration. Qualification timer value = qual_timer * dsqual_timer. 0 = 4x 1 = 2x 2 = 8x...
  • Page 139 8A3xxxx Family Programming Guide REF_MON_0.IN_MON_LOS_CFG Gap and margin configuration. Table 170: REF_MON_0.IN_MON_LOS_CFG Bit Field Locations and Descriptions Offset REF_MON_0.IN_MON_LOS_CFG Bit Field Locations Address (Hex) 00Ah RESERVED[7:3] LOS_GAP[2:1] LOS_MARGI N[0] REF_MON_0.IN_MON_LOS_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 140 8A3xxxx Family Programming Guide REF_MON_0.IN_MON_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DIV_OR_NON_DIV_CLK_ Select the divided clock or the non-divided clock as an input for the reference SELECT[5] monitor.
  • Page 141 8A3xxxx Family Programming Guide Table 172: DPLL_0 Register Index Register Module Base Address: C3B0h Offset (Hex) Individual Register Name Register Description 006h DPLL_0.DPLL_FILTER_STATUS_UPDATE_CF DPLL loop filter status update configuration. 007h DPLL_0.DPLL_HO_ADVCD_HISTORY Advanced holdover history configuration. 008h DPLL_0.DPLL_HO_ADVCD_BW DPLL advanced holdover bandwidth configuration. 00Ah DPLL_0.DPLL_HO_CFG Holdover configuration.
  • Page 142 8A3xxxx Family Programming Guide Table 172: DPLL_0 Register Index Register Module Base Address: C3B0h Offset (Hex) Individual Register Name Register Description 028h DPLL_0.DPLL_FASTLOCK_FSL Fast lock frequency slope limit. 02Ah DPLL_0.DPLL_FASTLOCK_BW Fast lock loop filter bandwidth. 02Ch DPLL_0.DPLL_WRITE_FREQ_TIMER Write frequency timer. 02Eh DPLL_0.DPLL_WRITE_PHASE_TIMER Write phase timer.
  • Page 143 8A3xxxx Family Programming Guide DPLL_0.DPLL_CTRL_0 Enable revertive switching, hitless switching and global sync mode. Table 174: DPLL_0.DPLL_CTRL_0 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_CTRL_0 Bit Field Locations Address (Hex) 002h FORCE_LOCK_INPUT[7:3] GLOBAL_SY REVERTIVE HITLESS_E NC_EN[2] _EN[1] N[0] DPLL_0.DPLL_CTRL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 144 8A3xxxx Family Programming Guide DPLL_0.DPLL_CTRL_1 Enable and select feedback clock. Table 175: DPLL_0.DPLL_CTRL_1 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_CTRL_1 Bit Field Locations Address (Hex) 003h RESERVED[7:5] FB_SELECT_REF[4:1] FB_SELECT _REF_EN[0] DPLL_0.DPLL_CTRL_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 145 8A3xxxx Family Programming Guide DPLL_0.DPLL_CTRL_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description FRAME_SYNC_PULSE_R Enable frame pulse or sync pulse periodic re-synchronization in locked state. ESYNC_EN[7] 0 = disabled 1 = enabled FRAME_SYNC_MODE[6:5 Select frame pulse mode or sync pulse mode. 0 = disabled 1 = frame pulse mode 2 = sync pulse mode...
  • Page 146 8A3xxxx Family Programming Guide DPLL_0.DPLL_UPDATE_RATE_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value UPDATE_RATE_CFG[1:0] DPLL loop filter update rate configuration. Used to avoid spurs at a specific frequency. 0 = 2.777 MHz 1 = 694 kHz 2 = 174 kHz...
  • Page 147 8A3xxxx Family Programming Guide DPLL_0.DPLL_HO_ADVCD_HISTORY Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value HISTORY[5:0] Configure DPLL holdover history. DPLL_0.DPLL_HO_ADVCD_BW DPLL advanced holdover bandwidth configuration. Table 180: DPLL_0.DPLL_HO_ADVCD_BW Bit Field Locations and Descriptions Offset DPLL_0.DPLL_HO_ADVCD_BW Bit Field Locations Address...
  • Page 148 8A3xxxx Family Programming Guide DPLL_0.DPLL_HO_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value HOLDOVER_MODE[2:0] Holdover type configuration. simple: holds DPLL with latest integrator value manual: holds DPLL with value from DPLL_CTRL_n.DPLL_MANUAL_HOLDOVER_VALUE advanced: holds DPLL with value derived from filtered DPLL frequency history 0 = simple...
  • Page 149 8A3xxxx Family Programming Guide DPLL_0.DPLL_LOCK_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description PHASE_MON_DUR[7:0] Duration of phase error monitoring before lock is declared, in seconds. 0 means 4000 microseconds. DPLL_0.DPLL_LOCK_2 Frequency lock threshold. Table 184: DPLL_0.DPLL_LOCK_2 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_LOCK_2 Bit Field Locations Address...
  • Page 150 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_0 Lowest priority index is highest priority. Table 186: DPLL_0.DPLL_REF_PRIORITY_0 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_0 Bit Field Locations Address (Hex) 00Fh PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 151 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_1 Lower priority index is higher priority. Table 187: DPLL_0.DPLL_REF_PRIORITY_1 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_1 Bit Field Locations Address (Hex) 010h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 152 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_2 Lower priority index is higher priority. Table 188: DPLL_0.DPLL_REF_PRIORITY_2 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_2 Bit Field Locations Address (Hex) 011h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 153 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_3 Lower priority index is higher priority. Table 189: DPLL_0.DPLL_REF_PRIORITY_3 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_3 Bit Field Locations Address (Hex) 012h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_3 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 154 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_4 Lower priority index is higher priority. Table 190: DPLL_0.DPLL_REF_PRIORITY_4 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_4 Bit Field Locations Address (Hex) 013h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_4 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 155 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_5 Lower priority index is higher priority. Table 191: DPLL_0.DPLL_REF_PRIORITY_5 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_5 Bit Field Locations Address (Hex) 014h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_5 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 156 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_6 Lower priority index is higher priority. Table 192: DPLL_0.DPLL_REF_PRIORITY_6 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_6 Bit Field Locations Address (Hex) 015h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_6 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 157 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_7 Lower priority index is higher priority. Table 193: DPLL_0.DPLL_REF_PRIORITY_7 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_7 Bit Field Locations Address (Hex) 016h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_7 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 158 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_8 Lower priority index is higher priority. Table 194: DPLL_0.DPLL_REF_PRIORITY_8 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_8 Bit Field Locations Address (Hex) 017h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_8 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 159 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_9 Lower priority index is higher priority. Table 195: DPLL_0.DPLL_REF_PRIORITY_9 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_9 Bit Field Locations Address (Hex) 018h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_9 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 160 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_10 Lower priority index is higher priority. Table 196: DPLL_0.DPLL_REF_PRIORITY_10 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_10 Bit Field Locations Address (Hex) 019h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_10 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 161 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_11 Lower priority index is higher priority. Table 197: DPLL_0.DPLL_REF_PRIORITY_11 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_11 Bit Field Locations Address (Hex) 01Ah PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_11 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 162 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_12 Lower priority index is higher priority. Table 198: DPLL_0.DPLL_REF_PRIORITY_12 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_12 Bit Field Locations Address (Hex) 01Bh PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_12 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 163 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_13 Lower priority index is higher priority. Table 199: DPLL_0.DPLL_REF_PRIORITY_13 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_13 Bit Field Locations Address (Hex) 01Ch PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_13 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 164 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_14 Lower priority index is higher priority. Table 200: DPLL_0.DPLL_REF_PRIORITY_14 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_14 Bit Field Locations Address (Hex) 01Dh PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_14 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 165 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_15 Lower priority index is higher priority. Table 201: DPLL_0.DPLL_REF_PRIORITY_15 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_15 Bit Field Locations Address (Hex) 01Eh PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_15 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 166 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_16 Lower priority index is higher priority. Table 202: DPLL_0.DPLL_REF_PRIORITY_16 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_16 Bit Field Locations Address (Hex) 01Fh PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_16 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 167 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_17 Highest priority index is lowest priority. Table 203: DPLL_0.DPLL_REF_PRIORITY_17 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_17 Bit Field Locations Address (Hex) 020h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_17 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 168 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_PRIORITY_18 Highest priority index is lowest priority. Table 204: DPLL_0.DPLL_REF_PRIORITY_18 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_PRIORITY_18 Bit Field Locations Address (Hex) 021h PRIORITY_GROUP_NUMBE PRIORITY_REF[5:1] PRIORITY_E R[7:6] N[0] DPLL_0.DPLL_REF_PRIORITY_18 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number.
  • Page 169 8A3xxxx Family Programming Guide 4. Fast acquisition - bandwidth is set to DPLL_FASTLOCK_BW until lock achieved Table 205: DPLL_0.DPLL_FASTLOCK_CFG_0 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_FASTLOCK_CFG_0 Bit Field Locations Address (Hex) 023h LOCK_REC_ LOCK_REC_ LOCK_REC_ LOCK_REC_ LOCK_ACQ_ LOCK_ACQ_ LOCK_ACQ_ LOCK_ACQ_ OL_PULL_IN FAST_ACQ_ PHASE_SNA...
  • Page 170 8A3xxxx Family Programming Guide DPLL_0.DPLL_FASTLOCK_CFG_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description LOCK_ACQ_PHASE_SNA Enable phase snap for LOCKACQ state. P_EN[1] When lock_acq_ol_pull_in_en is also enabled, instead phase snap, open loop phase pull-in will be performed. 0 = disabled 1 = enabled LOCK_ACQ_FREQ_SNAP Enable frequency snap for LOCKACQ state.
  • Page 171 8A3xxxx Family Programming Guide DPLL_0.DPLL_MAX_FREQ_OFFSET DPLL maximum frequency offset limit Table 207: DPLL_0.DPLL_MAX_FREQ_OFFSET Bit Field Locations and Descriptions Offset DPLL_0.DPLL_MAX_FREQ_OFFSET Bit Field Locations Address (Hex) 025h MAX_FFO[7:0] DPLL_0.DPLL_MAX_FREQ_OFFSET Bit Field Descriptions Bit Field Name Field Type Default Value Description MAX_FFO[7:0] Unsigned 8-bit maximum frequency offset limit in ppm.
  • Page 172 8A3xxxx Family Programming Guide DPLL_0.DPLL_FASTLOCK_FSL Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL_FASTLOCK_FSL[15 Unsigned 16-bit frequency slope limit in ppb/s. Value 0 implies no frequency slope limit. Applied only on frequency snap. DPLL_0.DPLL_FASTLOCK_BW Fast lock loop filter bandwidth. Table 210: DPLL_0.DPLL_FASTLOCK_BW Bit Field Locations and Descriptions Offset DPLL_0.DPLL_FASTLOCK_BW Bit Field Locations...
  • Page 173 8A3xxxx Family Programming Guide DPLL_0.DPLL_WRITE_FREQ_TIMER Bit Field Descriptions Bit Field Name Field Type Default Value Description WRITE_FREQ_TIMEOUT_ Unsigned 16-bit write frequency timeout value in milliseconds. CNFG[15:0] When in write frequency mode, the DPLL_WR_FREQ must be periodically written to within WRITE_FREQ_TIMEOUT_CNFG ms. If the write frequency timer expires, the write frequency as a reference is disqualified.
  • Page 174 8A3xxxx Family Programming Guide DPLL_0.DPLL_PRED_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value WP_PRED[1] Predefined configuration to be used for write phase input. Write phase predefined configuration selection (0 or 1). 0 = pred0 1 = pred1 PRED_EN[0]...
  • Page 175 8A3xxxx Family Programming Guide DPLL_0.DPLL_COMBO_SLAVE_CFG_0 Combo mode slave primary source configuration. Table 215: DPLL_0.DPLL_COMBO_SLAVE_CFG_0 Bit Field Locations and Descriptions Offset DPLL_0.DPLL_COMBO_SLAVE_CFG_0 Bit Field Locations Address (Hex) 032h RESERVED[7:6] PRI_COMBO PRI_COMBO PRI_COMBO_SRC_ID[3:0] _SRC_EN[5] _SRC_FILTE RED_CNFG[ DPLL_0.DPLL_COMBO_SLAVE_CFG_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED...
  • Page 176 8A3xxxx Family Programming Guide DPLL_0.DPLL_COMBO_SLAVE_CFG_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description SEC_COMBO_SRC_FILT Use filtered source. ERED_CNFG[4] 0 = use un-filtered source 1 = use filtered source SEC_COMBO_SRC_ID[3: Secondary combo source DPLL index. DPLL_0.DPLL_SLAVE_REF_CFG Slave mode configuration. Table 217: DPLL_0.DPLL_SLAVE_REF_CFG Bit Field Locations and Descriptions Offset DPLL_0.DPLL_SLAVE_REF_CFG Bit Field Locations...
  • Page 177 8A3xxxx Family Programming Guide DPLL_0.DPLL_REF_MODE Reference selection configuration. Table 218: DPLL_0.DPLL_REF_MODE Bit Field Locations and Descriptions Offset DPLL_0.DPLL_REF_MODE Bit Field Locations Address (Hex) 035h RESERVED[7:4] MODE[3:0] DPLL_0.DPLL_REF_MODE Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value MODE[3:0] Reference selection mode.
  • Page 178 8A3xxxx Family Programming Guide DPLL_0.DPLL_PHASE_MEASUREMENT_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description PFD_FB_CLK_SEL[7:4] Select the feedback clock going into the phase detector. The feedback clock selected must have the same frequency as the reference clock selected. 0x0 = CLK0 0x1 = CLK1 0x2 = CLK2...
  • Page 179 8A3xxxx Family Programming Guide Table 220: DPLL_0.DPLL_MODE Bit Field Locations and Descriptions Offset DPLL_0.DPLL_MODE Bit Field Locations Address (Hex) 037h RESERVED[ WRITE_TIM PLL_MODE[5:3] STATE_MODE[2:0] ER_MODE[6] DPLL_0.DPLL_MODE Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value WRITE_TIMER_MODE[6] Write phase or write frequency timer mode.
  • Page 180 8A3xxxx Family Programming Guide Note: The order of configuring three SCSR modules, SCSR_SYS_DPLL_XO, SCSR_SYS_APLL, SCSR_SYS_DPLL, are critical. The correct configuration order should be: SCSR_SYS_DPLL_XO, SCSR_SYS_APLL, SCSR_SYS_DPLL, and followed by other modules. Each of these three SCSR modules should be configured completely before configuring the next module. Table 221: SYS_DPLL Register Index Register Module Base Address: C5B8h Offset...
  • Page 181 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_CTRL_0 Reference switching configuration and forced lock reference selection. Table 222: SYS_DPLL.SYS_DPLL_CTRL_0 Bit Field Locations and Descriptions Offset SYS_DPLL.SYS_DPLL_CTRL_0 Bit Field Locations Address (Hex) 000h FORCE_LOCK_INPUT[7:3] RESERVED[ REVERTIVE RESERVED[ _EN[1] SYS_DPLL.SYS_DPLL_CTRL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description FORCE_LOCK_INPUT[7:3...
  • Page 182 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_UPDATE_RATE_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value UPDATE_RATE_CFG[1:0] System DPLL loop filter update rate configuration. Used to avoid spurs at a specific frequency. 0 = 2.777 MHz 1 = 694 kHz 2 = 174 kHz...
  • Page 183 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_LOCK_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description PHASE_UNIT[7:6] Phase lock threshold unit. 0 = 1 ns 1 = 10 ns 2 = 100 ns 3 = 1 us PHASE_LOCK_MAX_ERR Phase lock threshold value. OR[5:0] If 0, then Fractional Frequency Offset check is disabled.
  • Page 184 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_LOCK_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description FFO_UNIT[7:6] FFO error unit. 0 = 1 ppb 1 = 10 ppb 2 = 100 ppb 3 = 1 ppm FFO_LOCK_MAX_ERROR Integer maximum FFO error for lock criteria. [5:0] If 0, then Fractional Frequency Offset check is disabled.
  • Page 185 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] Used to group multiple clocks as equal priority. References in the same priority group number use non-revertive switching. PRIORITY_REF[5:1] Input reference index for priority 0.
  • Page 186 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 1. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 187 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 2. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 188 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_3 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 3. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 189 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_4 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 4. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 190 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_5 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 5. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 191 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_6 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 6. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 192 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_7 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 7. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 193 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_8 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 8. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 194 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_9 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 9. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 195 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_10 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 10. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 196 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_11 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 11. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 197 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_12 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 12. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 198 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_13 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 13. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 199 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_14 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 14. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 200 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_15 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 15. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 201 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_16 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 16. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 202 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_17 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 17. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 203 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_REF_PRIORITY_18 Bit Field Descriptions Bit Field Name Field Type Default Value Description PRIORITY_GROUP_NUM Priority group number. BER[7:6] For references in the same priority group, revertive switching is disabled. PRIORITY_REF[5:1] Input reference index for priority 18. 0x00 = CLK0 0x01 = CLK1 0x02 = CLK2 0x03 = CLK3...
  • Page 204 8A3xxxx Family Programming Guide SYS_DPLL.SYS_DPLL_MODE Select state machine transition mode. TRIGGER: Writing to this byte triggers a read and activation in hardware of all the bytes of the system DPLL module. Table 249: SYS_DPLL.SYS_DPLL_MODE Bit Field Locations and Descriptions Offset SYS_DPLL.SYS_DPLL_MODE Bit Field Locations Address (Hex)
  • Page 205 8A3xxxx Family Programming Guide Table 250: DPLL_CTRL_0 Register Index Register Module Base Address: C600h Offset (Hex) Individual Register Name Register Description 00Fh DPLL_CTRL_0.DPLL_PRED1_DECIMATOR_B Predefined configuration 1 loop filter decimator bandwidth multiplier. W_MULT 010h DPLL_CTRL_0.DPLL_PRED1_BW Predefined configuration 1 loop filter bandwidth. 012h DPLL_CTRL_0.DPLL_PRED1_PSL Predefined configuration 1 loop filter phase slope limit.
  • Page 206 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_MANU_REF_CFG Select reference to be used for manual reference selection mode. Table 252: DPLL_CTRL_0.DPLL_MANU_REF_CFG Bit Field Locations and Descriptions Offset DPLL_CTRL_0.DPLL_MANU_REF_CFG Bit Field Locations Address (Hex) 001h RESERVED[7:5] MANUAL_REFERENCE[4:0] DPLL_CTRL_0.DPLL_MANU_REF_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED...
  • Page 207 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_DAMPING Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DAMP_FTR[3:0] DPLL loop filter damping factor. 0 = 1.002, 0.02 dB, overdamp; 1 = 1.006, 0.05 dB, < 0.05 dB; 2 = 1.008, 0.07 dB, <...
  • Page 208 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] DPLL loop filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz DPLL_BW[13:0] Unsigned 14-bit DPLL loop filter bandwidth value. DPLL_CTRL_0.DPLL_PSL DPLL loop filter phase slope limit.
  • Page 209 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_PRED0_DAMPING Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DAMP_FTR[3:0] DPLL loop filter damping factor. 0 = 1.002, 0.02 dB, overdamp; 1 = 1.006, 0.05 dB, < 0.05 dB; 2 = 1.008, 0.07 dB, <...
  • Page 210 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_PRED0_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] DPLL loop filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz DPLL_PRED0_BW[13:0] Unsigned 14-bit DPLL loop filter bandwidth value. DPLL_CTRL_0.DPLL_PRED0_PSL Predefined configuration 0 loop filter phase slope limit.
  • Page 211 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_PRED1_DAMPING Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DAMP_FTR[3:0] DPLL loop filter damping factor. 0 = 1.002, 0.02 dB, overdamp; 1 = 1.006, 0.05 dB, < 0.05 dB; 2 = 1.008, 0.07 dB, <...
  • Page 212 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_PRED1_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] DPLL loop filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz DPLL_PRED1_BW[13:0] Unsigned 14-bit DPLL loop filter bandwidth value. DPLL_CTRL_0.DPLL_PRED1_PSL Predefined configuration 1 loop filter phase slope limit.
  • Page 213 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_PHASE_OFFSET_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL_PHASE_OFFSET_ Signed 36-bit phase offset in ITDC_UIs. CFG[35:0] ITDC_UI is input TDC unit interval. Please refer to the SCSR_INPUT_TDC module for details on input TDC settings and ITDC_UI value.
  • Page 214 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_FINE_PHASE_ADV_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value FINE_PHASE_ADVANCE[ Unsigned (i.e. positive) 13-bit fine phase advance. 12:0] Note: This register must be set to 0 if the DPLL feedback clock has a fractional component.
  • Page 215 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_FOD_FREQ Bit Field Descriptions Bit Field Name Field Type Default Value Description N[15:0] Unsigned 16-bit frequency N field. N must not be configured to 0. M[47:0] Unsigned 48-bit frequency M field. A setting of 0 will disable the FOD, but not other parts of the DPLL. This will significantly reduce the power consumption of this DPLL.
  • Page 216 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_COMBO_SW_VALUE_CNFG DCO value to be added to the combo bus in SW combo mode. Table 270: DPLL_CTRL_0.DPLL_COMBO_SW_VALUE_CNFG Bit Field Locations and Descriptions Offset DPLL_CTRL_0.DPLL_COMBO_SW_VALUE_CNFG Bit Field Locations Address (Hex) 028h DPLL_COMBO_SW_VALUE_CNFG[7:0] 029h DPLL_COMBO_SW_VALUE_CNFG[15:8] 02Ah DPLL_COMBO_SW_VALUE_CNFG[23:16] 02Bh DPLL_COMBO_SW_VALUE_CNFG[31:24] 02Ch DPLL_COMBO_SW_VALUE_CNFG[39:32]...
  • Page 217 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_DCD_FILTER_CNFG DPLL DCD filter configuration. Table 272: DPLL_CTRL_0.DPLL_DCD_FILTER_CNFG Bit Field Locations and Descriptions Offset DPLL_CTRL_0.DPLL_DCD_FILTER_CNFG Bit Field Locations Address (Hex) 036h DCD_MANU_UPDATE_RAT DCD_MANU_GAIN_SHIFT[5:1] DCD_MANU E_CNFG[7:6] _EN[0] 037h RESERVED[ DCD_LPF_COE[14:10] DCD_MANU_UPDATE_RAT E_CNFG[9:8] DPLL_CTRL_0.DPLL_DCD_FILTER_CNFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED...
  • Page 218 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_COMBO_MASTER_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] Combo filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz DPLL_COMBO_MASTER_ Unsigned 14-bit Combo filter bandwidth value. BW[13:0] DPLL_CTRL_0.DPLL_COMBO_MASTER_CFG DPLL combo master configuration.
  • Page 219 8A3xxxx Family Programming Guide DPLL_CTRL_0.DPLL_FRAME_PULSE_SYNC Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value FRAME_PULSE_SYNC[0] Trigger a frame pulse sync Write 1 to trigger a frame pulse sync procedure. This bit will be self-cleared after the sync finished.
  • Page 220 8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_MANU_REF_CFG Select reference to be used for manual reference selection mode. Table 277: SYS_DPLL_CTRL.SYS_DPLL_MANU_REF_CFG Bit Field Locations and Descriptions Offset SYS_DPLL_CTRL.SYS_DPLL_MANU_REF_CFG Bit Field Locations Address (Hex) 000h RESERVED[7:5] MANUAL_REFERENCE[4:0] SYS_DPLL_CTRL.SYS_DPLL_MANU_REF_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED...

  • Page 221: Sys_Dpll_Ctrl.sys_Dpll_Decimator_Bw_Mult

    8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_DAMPING Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DAMP_FTR[3:0] System DPLL loop filter damping factor 0 = 1.002, 0.02 dB, overdamp; 1 = 1.006, 0.05 dB, <...

  • Page 222: Sys_Dpll_Ctrl.sys_Dpll_Psl

    8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] System DPLL loop filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz SYS_DPLL_BW[13:0] Unsigned 14-bit system DPLL loop filter bandwidth value. SYS_DPLL_CTRL.SYS_DPLL_PSL System DPLL loop filter phase slope limit.

  • Page 223: Ator_Bw_Mult

    8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_PRED0_DAMPING Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DAMP_FTR[3:0] System DPLL loop filter damping factor. 0 = 1.002, 0.02 dB, overdamp; 1 = 1.006, 0.05 dB, <...

  • Page 224: Sys_Dpll_Ctrl.sys_Dpll_Pred0_Psl

    8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_PRED0_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] System DPLL loop filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz SYS_DPLL_PRED0_BW[1 Unsigned 14-bit system DPLL loop filter bandwidth value. 3:0] SYS_DPLL_CTRL.SYS_DPLL_PRED0_PSL Predefined configuration 0 loop filter phase slope limit.

  • Page 225: Sys_Dpll_Ctrl.sys_Dpll_Pred1_Bw

    8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_PRED1_DAMPING Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DAMP_FTR[3:0] System DPLL loop filter damping factor. 0 = 1.002, 0.02 dB, overdamp; 1 = 1.006, 0.05 dB, <...

  • Page 226: Sys_Dpll_Ctrl.sys_Dpll_Pred1_Psl

    8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_PRED1_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] System DPLL loop filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz SYS_DPLL_PRED1_BW[1 Unsigned 14-bit system DPLL loop filter bandwidth value. 3:0] SYS_DPLL_CTRL.SYS_DPLL_PRED1_PSL Predefined configuration 1 loop filter phase slope limit.
  • Page 227 8A3xxxx Family Programming Guide SYS_DPLL_CTRL.SYS_DPLL_COMBO_MASTER_BW Bit Field Descriptions Bit Field Name Field Type Default Value Description BW_UNIT[15:14] Combo filter bandwidth unit. 0 = uHz 1 = mHz 2 = Hz 3 = kHz SYS_DPLL_COMBO_MAS Unsigned 14-bit Combo filter bandwidth value. TER_BW[13:0] SYS_DPLL_CTRL.SYS_DPLL_COMBO_MASTER_CFG DPLL combo master configuration.
  • Page 228 8A3xxxx Family Programming Guide DPLL_PHASE_0.DPLL_WRITE_PH Set phase offset in write phase mode. Table 293: DPLL_PHASE_0.DPLL_WRITE_PH Bit Field Locations and Descriptions Offset DPLL_PHASE_0.DPLL_WRITE_PH Bit Field Locations Address (Hex) 000h DPLL_WRITE_PH[7:0] 001h DPLL_WRITE_PH[15:8] 002h DPLL_WRITE_PH[23:16] 003h DPLL_WRITE_PH[31:24] DPLL_PHASE_0.DPLL_WRITE_PH Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL_WRITE_PH[31:0]...
  • Page 229 8A3xxxx Family Programming Guide DPLL_FREQ_0.DPLL_WR_FREQ Set DPLL frequency offset in write frequency mode. Table 295: DPLL_FREQ_0.DPLL_WR_FREQ Bit Field Locations and Descriptions Offset DPLL_FREQ_0.DPLL_WR_FREQ Bit Field Locations Address (Hex) 000h DPLL_WR_FREQ[7:0] 001h DPLL_WR_FREQ[15:8] 002h DPLL_WR_FREQ[23:16] 003h DPLL_WR_FREQ[31:24] 004h DPLL_WR_FREQ[39:32] 005h RESERVED[47:42] DPLL_WR_FREQ[41:40] DPLL_FREQ_0.DPLL_WR_FREQ Bit Field Descriptions Bit Field Name...
  • Page 230 8A3xxxx Family Programming Guide DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET Phase pull-in offset. Table 297: DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET Bit Field Locations and Descriptions Offset DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET Bit Field Locations Address (Hex) 000h DPLL_PHASE_PULL_IN_OFFSET[7:0] 001h DPLL_PHASE_PULL_IN_OFFSET[15:8] 002h DPLL_PHASE_PULL_IN_OFFSET[23:16] 003h DPLL_PHASE_PULL_IN_OFFSET[31:24] DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_OFFSET Bit Field Descriptions Bit Field Name Field Type Default Value Description DPLL_PHASE_PULL_IN_ Signed 32-bit phase pull-in offset in nanoseconds.
  • Page 231 8A3xxxx Family Programming Guide DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_CTRL Phase pull-in configuration. Table 299: DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_CTRL Bit Field Locations and Descriptions Offset DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_CTRL Bit Field Locations Address (Hex) 007h RESERVED[7:1] PHASE_PUL L_IN_REQU EST[0] DPLL_PHASE_PULL_IN_0.DPLL_PHASE_PULL_IN_CTRL Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value PHASE_PULL_IN_REQUE...
  • Page 232 8A3xxxx Family Programming Guide GPIO_CFG.GPIO_CFG_GBL Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value SUPPLY_MODE[1:0] Select GPIO supply rail configuration. Select GPIO drive voltage. 0 = 1.8 V 1 = 2.5 V/3.3 V 2 = 1.5 V Module: GPIO_0...
  • Page 233 8A3xxxx Family Programming Guide GPIO_0.GPIO_DCO_INC_DEC Increment/decrement DCO FFO configuration. Applies when GPIO_FUNCTION is equal to 'inc DCO FFO' or 'dec DCO FFO'. The squelch level is determined by the configuration per output by OUTPUT_n.OUT_CTR_1.SQUELCH_VALUE. Table 303: GPIO_0.GPIO_DCO_INC_DEC Bit Field Locations and Descriptions Offset GPIO_0.GPIO_DCO_INC_DEC Bit Field Locations Address...
  • Page 234 8A3xxxx Family Programming Guide GPIO_0.GPIO_OUT_CTRL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description CTRL_OUT_7[7] Select output 7 to be controlled by this GPIO. GPIO is used to disable (squelch) output 7. 0 = disabled 1 = enabled CTRL_OUT_6[6] Select output 6 to be controlled by this GPIO.
  • Page 235 8A3xxxx Family Programming Guide GPIO_0.GPIO_OUT_CTRL_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value CTRL_OUT_11[3] Select output 11 to be controlled by this GPIO. GPIO is used to disable (squelch) output 11. 0 = disabled 1 = enabled CTRL_OUT_10[2]...
  • Page 236 8A3xxxx Family Programming Guide GPIO_0.GPIO_TOD_TRIG Bit Field Descriptions Bit Field Name Field Type Default Value Description TOD_TRIG_2[2] Select TOD of DPLL 2 to be triggered by this GPIO. The TOD read/write operation is triggered on the rising edge of this GPIO. The tod_write_selection or tod_read_trigger for TOD 2 has to be equal to 'Selected GPIO'.
  • Page 237 8A3xxxx Family Programming Guide GPIO_0.GPIO_DPLL_INDICATOR Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value DPLL_INDEX[3:0] DPLL index used by lock indicator or holdover indicator function. The GPIO level is active when the DPLL is in locked state when GPIO_n.GPIO_FUNCTION = lock indicator.
  • Page 238 8A3xxxx Family Programming Guide GPIO_0.GPIO_REF_INPUT_DSQ_0 Select the set of inputs to be disqualified when the GPIO is at the configured level. Applies when GPIO_FUNCTION is equal to 'input clock disqualify'. Table 309: GPIO_0.GPIO_REF_INPUT_DSQ_0 Bit Field Locations and Descriptions Offset GPIO_0.GPIO_REF_INPUT_DSQ_0 Bit Field Locations Address (Hex) 006h...
  • Page 239 8A3xxxx Family Programming Guide GPIO_0.GPIO_REF_INPUT_DSQ_1 Select the set of inputs to be disqualified when the GPIO is at the configured level. Applies when GPIO_FUNCTION is equal to 'input clock disqualify'. Table 310: GPIO_0.GPIO_REF_INPUT_DSQ_1 Bit Field Locations and Descriptions Offset GPIO_0.GPIO_REF_INPUT_DSQ_1 Bit Field Locations Address (Hex) 007h...
  • Page 240 8A3xxxx Family Programming Guide GPIO_0.GPIO_REF_INPUT_DSQ_2 Select the set of DPLLs to have inputs disqualified when the GPIO is at the configured level. Applies when GPIO_FUNCTION is equal to 'input clock disqualify'. Table 311: GPIO_0.GPIO_REF_INPUT_DSQ_2 Bit Field Locations and Descriptions Offset GPIO_0.GPIO_REF_INPUT_DSQ_2 Bit Field Locations Address (Hex)
  • Page 241 8A3xxxx Family Programming Guide GPIO_0.GPIO_REF_INPUT_DSQ_3 Select the system DPLL to have its input disqualified when the GPIO is at the configured level. Applies when GPIO_FUNCTION is equal to 'input clock disqualify'. Table 312: GPIO_0.GPIO_REF_INPUT_DSQ_3 Bit Field Locations and Descriptions Offset GPIO_0.GPIO_REF_INPUT_DSQ_3 Bit Field Locations Address (Hex)
  • Page 242 8A3xxxx Family Programming Guide GPIO_0.GPIO_MAN_CLK_SEL_1 Applies when GPIO_FUNCTION is equal to 'manual clock select'. Table 314: GPIO_0.GPIO_MAN_CLK_SEL_1 Bit Field Locations and Descriptions Offset GPIO_0.GPIO_MAN_CLK_SEL_1 Bit Field Locations Address (Hex) 00Bh DPLL7[7] DPLL6[6] DPLL5[5] DPLL4[4] DPLL3[3] DPLL2[2] DPLL1[1] DPLL0[0] GPIO_0.GPIO_MAN_CLK_SEL_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 243 8A3xxxx Family Programming Guide GPIO_0.GPIO_MAN_CLK_SEL_2 Applies when GPIO_FUNCTION is equal to 'manual clock select'. Table 315: GPIO_0.GPIO_MAN_CLK_SEL_2 Bit Field Locations and Descriptions Offset GPIO_0.GPIO_MAN_CLK_SEL_2 Bit Field Locations Address (Hex) 00Ch RESERVED[7:1] DPLL_SYS[0 GPIO_0.GPIO_MAN_CLK_SEL_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 244 8A3xxxx Family Programming Guide GPIO_0.GPIO_ALERT_OUT_CFG Configure the GPIO alert active level. Table 317: GPIO_0.GPIO_ALERT_OUT_CFG Bit Field Locations and Descriptions Offset GPIO_0.GPIO_ALERT_OUT_CFG Bit Field Locations Address (Hex) 00Eh RESERVED[7:1] GPIO_ALER T_OUT_LEV EL[0] GPIO_0.GPIO_ALERT_OUT_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 245 8A3xxxx Family Programming Guide GPIO_0.GPIO_TOD_NOTIFICATION_CFG Bit Field Descriptions Bit Field Name Field Type Default Value Description TOD_READ_SECONDAR Select the primary or secondary TOD read registers. Y[2] The GPIO level becomes active after the TOD register is updated. 0 = ToD read primary 1 = ToD read secondary DPLL_TOD[1:0] DPLL TOD index.
  • Page 246 8A3xxxx Family Programming Guide GPIO_0.GPIO_CTRL Bit Field Descriptions Bit Field Name Field Type Default Value Description GPIO_FUNCTION[7:4] Select GPIO function. Selects which gpio function to perform. 0x0 = lock indicator (out) 0x1 = holdover indicator (out) 0x2 = LOS indicator (out) 0x3 = alert out (out) 0x4 = inc DCO FFO (in) 0x5 = dec DCO FFO (in)
  • Page 247 8A3xxxx Family Programming Guide OUT_DIV_MUX.OUT_DIV8_MUX Output divider 8 multiplexer configuration. Table 321: OUT_DIV_MUX.OUT_DIV8_MUX Bit Field Locations and Descriptions Offset OUT_DIV_MUX.OUT_DIV8_MUX Bit Field Locations Address (Hex) 000h RESERVED[7:1] FOD5_TO_O UT_DIV8[0] OUT_DIV_MUX.OUT_DIV8_MUX Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value...
  • Page 248 8A3xxxx Family Programming Guide Module: OUTPUT_0 TRIGGER: Every register in this module is a trigger register. In the case of a multibyte register the highest address register byte is the trigger byte. Table 323: OUTPUT_0 Register Index Register Module Base Address: CA14h Offset (Hex) Individual Register Name...
  • Page 249 8A3xxxx Family Programming Guide OUTPUT_0.OUT_DUTY_CYCLE_HIGH Sets the output duty cycle high value Table 325: OUTPUT_0.OUT_DUTY_CYCLE_HIGH Bit Field Locations and Descriptions Offset OUTPUT_0.OUT_DUTY_CYCLE_HIGH Bit Field Locations Address (Hex) 004h OUT_DUTY_CYCLE_HIGH[7:0] 005h OUT_DUTY_CYCLE_HIGH[15:8] 006h OUT_DUTY_CYCLE_HIGH[23:16] 007h OUT_DUTY_CYCLE_HIGH[31:24] OUTPUT_0.OUT_DUTY_CYCLE_HIGH Bit Field Descriptions Bit Field Name Field Type Default Value Description OUT_DUTY_CYCLE_HIG...
  • Page 250 8A3xxxx Family Programming Guide OUTPUT_0.OUT_CTRL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description PAD_VOS[7:5] Output common mode voltage. 0 = 0.9V 1 = 1.1V 2 = 1.3V 3 = 1.5V 4 = 1.7V 5 = 1.9V 6 = 2.1V 7 = 2.3V PAD_VSWING[4:3] Output single-ended voltage swing.
  • Page 251 8A3xxxx Family Programming Guide OUTPUT_0.OUT_CTRL_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description SQUELCH_DISABLE[5] Enable or disable output squelch. 0 = squelch enabled 1 = squelch disabled PAD_VDDO[4:2] VDDO level. 0 = 1.8V 1 = 3.3V 2 = 2.5V 3 = 1.5V 4 = 1.2V PAD_CMOSDRV[1:0]...
  • Page 252 8A3xxxx Family Programming Guide Module: SERIAL Configure the serial communication ports. Table 329: SERIAL Register Index Register Module Base Address: CAE0h Offset (Hex) Individual Register Name Register Description 000h SERIAL.I2CM I2C Master configuration. 001h RESERVED This register must not be modified from the read value 002h SERIAL.SER0 Slave serial interface 0 (main serial port) configuration.
  • Page 253 8A3xxxx Family Programming Guide SERIAL.SER0 Slave serial interface 0 (main serial port) configuration. Table 331: SERIAL.SER0 Bit Field Locations and Descriptions Offset SERIAL.SER0 Bit Field Locations Address (Hex) 002h RESERVED[7:3] ADDRESS_S MODE[1:0] IZE[2] SERIAL.SER0 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED...
  • Page 254 8A3xxxx Family Programming Guide SERIAL.SER0_SPI Bit Field Descriptions Bit Field Name Field Type Default Value Description SPI_DUPLEX_MODE[2] SPI 4-wire or 3-wire. Select either 4-wire full duplex mode or 3-wire half duplex mode. 0 = full duplex 1 = half duplex RESERVED This field must not be modified from the read value SERIAL.SER0_I2C...
  • Page 255 8A3xxxx Family Programming Guide SERIAL.SER1 Bit Field Descriptions Bit Field Name Field Type Default Value Description ADDRESS_SIZE[2] Serial interface 1 address size. 0 = 1-byte 1 = 2-byte MODE[1:0] Serial interface 1 mode. Set MODE = 0 to maintain current configuration (e.g. mode indicated by SER1_STATUS_MODE field will remain the same).
  • Page 256 8A3xxxx Family Programming Guide SERIAL.SER1_I2C I2C configuration for serial interface 1 (auxiliary serial port). Table 336: SERIAL.SER1_I2C Bit Field Locations and Descriptions Offset SERIAL.SER1_I2C Bit Field Locations Address (Hex) 007h APPLY[7] DEVICE_ADDRESS[6:0] SERIAL.SER1_I2C Bit Field Descriptions Bit Field Name Field Type Default Value Description APPLY[7] Apply the new I2C address when the confirmation code triggers configuration to...
  • Page 257 8A3xxxx Family Programming Guide Module: PWM_ENCODER_0 Configure the PWM encoder. Table 338: PWM_ENCODER_0 Register Index Register Module Base Address: CB00h Offset (Hex) Individual Register Name Register Description 000h PWM_ENCODER_0.PWM_ENCODER_ID PWM encoder identifier. 001h PWM_ENCODER_0.PWM_ENCODER_CNFG PWM encoder configuration. 002h PWM_ENCODER_0.PWM_ENCODER_SIGNA PWM encoder signature configuration. TURE_0 003h PWM_ENCODER_0.PWM_ENCODER_SIGNA...
  • Page 258 8A3xxxx Family Programming Guide PWM_ENCODER_0.PWM_ENCODER_CNFG Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value PPS_SEL[3] Select source to trigger transmission of PWM PPS frame. For dual-channel PWM encoders[0:3], a value of 0 means that TOD engine selected in tod_sel field is used as a trigger source, a value of 1 means that the output not used for PWM carrier is used as a trigger source.
  • Page 259 8A3xxxx Family Programming Guide PWM_ENCODER_0.PWM_ENCODER_SIGNATURE_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description FIFTH_SYMBOL[7:6] The fifth symbol of the signature. zero (25 on/75 off duty cycle clock period), one (75 on/25 off duty cycle clock period), space (50 on/50 off duty cycle clock period) 0 = zero 1 = one 2 = space...
  • Page 260 8A3xxxx Family Programming Guide PWM_ENCODER_0.PWM_ENCODER_SIGNATURE_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value FIRST_SYMBOL[6] The first symbol of the signature. zero (25 on/75 off duty cycle clock period), one (75 on/25 off duty cycle clock period) 0 = zero 1 = one...
  • Page 261 8A3xxxx Family Programming Guide PWM_ENCODER_0.PWM_ENCODER_CMD Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value TOD_TX[2] Enable TOD transmission. The TOD transmission can be enabled only if signature mode is disabled. 0 = disabled 1 = enabled SIGNATURE_MODE[1]...
  • Page 262 8A3xxxx Family Programming Guide PWM_DECODER_0.PWM_DECODER_CNFG Bit Field Descriptions Bit Field Name Field Type Default Value Description GENERATE_PPS[15] Generate PPS pulse. 0 = do not generate internal PPS 1 = generate internal PPS PPS_RATE[14:0] PWM PPS rate in units of 0.5 Hz. PWM_DECODER_0.PWM_DECODER_ID Unique identifier defined by user.
  • Page 263 8A3xxxx Family Programming Guide PWM_DECODER_0.PWM_DECODER_SIGNATURE_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description FIFTH_SYMBOL[7:6] The fifth symbol of the signature. zero (25 on/75 off duty cycle clock period), one (75 on/25 off duty cycle clock period), space (50 on/50 off duty cycle clock period) 0 = zero 1 = one 2 = space...
  • Page 264 8A3xxxx Family Programming Guide PWM_DECODER_0.PWM_DECODER_SIGNATURE_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value FIRST_SYMBOL[6] The first symbol of the signature. zero (25 on/75 off duty cycle clock period), one (75 on/25 off duty cycle clock period) 0 = zero 1 = one...
  • Page 265 8A3xxxx Family Programming Guide PWM_DECODER_0.PWM_DECODER_CMD Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value TOD_FRAME_ACCESS_E TOD frame external access enable N[2] When this bit of all PWM decoders (decoder 0 to decoder 15) are set to 0, the received TOD frame will be discarded immediately.
  • Page 266 8A3xxxx Family Programming Guide PWM_USER_DATA.PWM_DST_DECODER_ID The ID of the destination PWM decoder. Table 352: PWM_USER_DATA.PWM_DST_DECODER_ID Bit Field Locations and Descriptions Offset PWM_USER_DATA.PWM_DST_DECODER_ID Bit Field Locations Address (Hex) 001h DECODER_ID[7:0] PWM_USER_DATA.PWM_DST_DECODER_ID Bit Field Descriptions Bit Field Name Field Type Default Value Description DECODER_ID[7:0] PWM decoder identification.
  • Page 267 8A3xxxx Family Programming Guide PWM_USER_DATA.PWM_USER_DATA_CMD_STS Bit Field Descriptions Bit Field Name Field Type Default Value Description COMMAND_STATUS[7:0] The user must set this field to 'Idle' whenever it is ready to receive new data. Before transmitting, the user has to set the 'Tx request' command and then wait for the 'Tx ack'.
  • Page 268 8A3xxxx Family Programming Guide TRIGGER: Writing to this byte triggers a read and activation of all the bytes of the TOD module. Table 356: TOD_0.TOD_CFG Bit Field Locations and Descriptions Offset TOD_0.TOD_CFG Bit Field Locations Address (Hex) 000h RESERVED[7:3] TOD_EVEN_ TOD_OUT_S TOD_ENABL PPS_MODE[...
  • Page 269 8A3xxxx Family Programming Guide TOD_WRITE_0.TOD_WRITE The maximum frequency of the clock driving the TOD accumulator is 1 GHz for DPLL 0 and 1, and 770 MHz for DPLL 2 and 3 . Table 358: TOD_WRITE_0.TOD_WRITE Bit Field Locations and Descriptions Offset TOD_WRITE_0.TOD_WRITE Bit Field Locations Address...
  • Page 270 8A3xxxx Family Programming Guide TOD_WRITE_0.TOD_WRITE_COUNTER Bit Field Descriptions Bit Field Name Field Type Default Value Description WRITE_COUNTER[7:0] TOD write counter. This counter increments after the TOD is written to. TOD_WRITE_0.TOD_WRITE_SELECT_CFG_0 Select the PWM decoder or the input index used as a trigger for TOD write. Table 360: TOD_WRITE_0.TOD_WRITE_SELECT_CFG_0 Bit Field Locations and Descriptions Offset TOD_WRITE_0.TOD_WRITE_SELECT_CFG_0 Bit Field Locations...
  • Page 271 8A3xxxx Family Programming Guide TOD_WRITE_0.TOD_WRITE_CMD Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value TOD_WRITE_SELECTION TOD write trigger selection. [3:0] 0 = disabled, no trigger 1 = immediate 2 = selected reference clock input 3 = selected PWM decoder's 1 PPS output 4 = reserved...
  • Page 272 8A3xxxx Family Programming Guide Table 363: TOD_READ_PRIMARY_0.TOD_READ_PRIMARY Bit Field Locations and Descriptions Offset TOD_READ_PRIMARY_0.TOD_READ_PRIMARY Bit Field Locations Address (Hex) 004h NS[39:32] 005h SECONDS[47:40] 006h SECONDS[55:48] 007h SECONDS[63:56] 008h SECONDS[71:64] 009h SECONDS[79:72] 00Ah SECONDS[87:80] TOD_READ_PRIMARY_0.TOD_READ_PRIMARY Bit Field Descriptions Bit Field Name Field Type Default Value Description SECONDS[87:40]...
  • Page 273 8A3xxxx Family Programming Guide TOD_READ_PRIMARY_0.TOD_READ_PRIMARY_SEL_CFG_0 Select the PWM decoder or the input index used as a trigger for TOD read. Table 365: TOD_READ_PRIMARY_0.TOD_READ_PRIMARY_SEL_CFG_0 Bit Field Locations and Descriptions Offset TOD_READ_PRIMARY_0.TOD_READ_PRIMARY_SEL_CFG_0 Bit Field Locations Address (Hex) 00Ch PWM_DECODER_INDEX[7:4] REF_INDEX[3:0] TOD_READ_PRIMARY_0.TOD_READ_PRIMARY_SEL_CFG_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description...
  • Page 274 8A3xxxx Family Programming Guide TOD_READ_PRIMARY_0.TOD_READ_PRIMARY_CMD Bit Field Descriptions Bit Field Name Field Type Default Value Description TOD_READ_TRIGGER_M Select single shot TOD read or continuous TOD read. ODE[4] This field will be cleared after the first TOD read finish. 0 = single shot 1 = continuous TOD_READ_TRIGGER[3: Read TOD trigger.
  • Page 275 8A3xxxx Family Programming Guide TOD_READ_SECONDARY_0.TOD_READ_SECONDARY The maximum frequency of the clock driving the TOD accumulator is 1 GHz for DPLL 0 and 1, and 770 MHz for DPLL 2 and 3 . Table 368: TOD_READ_SECONDARY_0.TOD_READ_SECONDARY Bit Field Locations and Descriptions Offset TOD_READ_SECONDARY_0.TOD_READ_SECONDARY Bit Field Locations Address...
  • Page 276 8A3xxxx Family Programming Guide TOD_READ_SECONDARY_0.TOD_READ_SECONDARY_COUNTER Bit Field Descriptions Bit Field Name Field Type Default Value Description READ_COUNTER[7:0] TOD read counter. This counter increments after the TOD is read from. TOD_READ_SECONDARY_0.TOD_READ_SECONDARY_SEL_CFG_0 Select the PWM decoder or the input index used as a trigger for TOD read. Table 370: TOD_READ_SECONDARY_0.TOD_READ_SECONDARY_SEL_CFG_0 Bit Field Locations and Descriptions Offset...
  • Page 277 8A3xxxx Family Programming Guide TOD_READ_SECONDARY_0.TOD_READ_SECONDARY_CMD Bit Field Descriptions Bit Field Name Field Type Default Value Description TOD_READ_TRIGGER_M Select single shot TOD read or continuous TOD read. ODE[4] This field will be cleared after the first TOD read finish. 0 = single shot 1 = continuous TOD_READ_TRIGGER[3: Read TOD trigger.
  • Page 278 8A3xxxx Family Programming Guide OUTPUT_TDC_CFG.OUTPUT_TDC_CFG_GBL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description FAST_LOCK_ENABLE_D Duration to wait after enabling output TDC fast lock. ELAY[15:0] Unsigned 16-bit value in microseconds. 0 = default 500 microseconds. When output TDC is enabled, it needs time for the reference clock to settle to the correct frequency.
  • Page 279 8A3xxxx Family Programming Guide OUTPUT_TDC_CFG.OUTPUT_TDC_CFG_GBL_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description RESERVED This field must not be modified from the read value REF_SEL[1] Select reference clock for output TDC. ref_sel change takes effect when 'enable' transitions from 0 -> 1. If ref_sel is changed when 'enable' = 1, the change is ignored.
  • Page 280 8A3xxxx Family Programming Guide OUTPUT_TDC_0.OUTPUT_TDC_CTRL_0 Bit Field Descriptions Bit Field Name Field Type Default Value Description SAMPLES[15:0] Unsigned 16-bit value indicating the number of samples to use for measurement. 0 = 4096 samples. When using more than one sample, the final measurement is an average. OUTPUT_TDC_0.OUTPUT_TDC_CTRL_1 Configure output TDC.
  • Page 281 8A3xxxx Family Programming Guide OUTPUT_TDC_0.OUTPUT_TDC_CTRL_2 Bit Field Descriptions Bit Field Name Field Type Default Value Description ALIGN_TARGET_MASK[7: Used in alignment mode to indicate the target DPLL(s) to align with 'source_index'. DPLL alignment target mask index. Alignment mode: Each set bit represents the DPLLs to be aligned with the 'source_index' DPLL.
  • Page 282 8A3xxxx Family Programming Guide OUTPUT_TDC_0.OUTPUT_TDC_CTRL_3 Bit Field Descriptions Bit Field Name Field Type Default Value Description TARGET_INDEX[7:4] Used in measurement mode to indicate the target clock. Indicates the target to measure against 'source_index'. 0x0 = DPLL0 0x1 = DPLL1 0x2 = DPLL2 0x3 = DPLL3 0x4 = DPLL4 0x5 = DPLL5...
  • Page 283 8A3xxxx Family Programming Guide OUTPUT_TDC_0.OUTPUT_TDC_CTRL_4 Bit Field Descriptions Bit Field Name Field Type Default Value Description DISABLE_MEASUREMEN Large measurements are considered outliers and filtered out. T_FILTER[7] If 'source_index' is a DPLL index, measurements larger than 1/2 the master divider frequency are filtered out. To disable this filtering, set 'disable_measurement_filter' = 1.
  • Page 284 8A3xxxx Family Programming Guide OUTPUT_TDC_0.OUTPUT_TDC_CTRL_4 Bit Field Descriptions Bit Field Name Field Type Default Value Description MODE[1] Select mode of output TDC operation. Measurement mode: Take a measurement at approx. 100 us intervals. When 'samples' measurements is reached, the average measurement is stored it in OUTPUT_TDCn_MEASUREMENT.
  • Page 285 8A3xxxx Family Programming Guide INPUT_TDC.INPUT_TDC_FBD_CTRL Input TDC feedback divider control. Table 383: INPUT_TDC.INPUT_TDC_FBD_CTRL Bit Field Locations and Descriptions Offset INPUT_TDC.INPUT_TDC_FBD_CTRL Bit Field Locations Address (Hex) 004h FBD_INTEG FBD_INTEGER[6:0] ER_MODE_ EN[7] INPUT_TDC.INPUT_TDC_FBD_CTRL Bit Field Descriptions Bit Field Name Field Type Default Value Description FBD_INTEGER_MODE_E Input TDC feedback divider integer mode enable.
  • Page 286 8A3xxxx Family Programming Guide Module: SCRATCH These multipurpose registers are not used by FW and are intended to for users to maintain their own data. Table 385: SCRATCH Register Index Register Module Base Address: CF50h Offset (Hex) Individual Register Name Register Description 000h SCRATCH.SCRATCH0...
  • Page 287 8A3xxxx Family Programming Guide SCRATCH.SCRATCH1 Bit Field Descriptions Bit Field Name Field Type Default Value Description SCRATCH1[31:0] User data. SCRATCH.SCRATCH2 User read or write data. The HW reset value will be restored on soft reset. Table 388: SCRATCH.SCRATCH2 Bit Field Locations and Descriptions Offset SCRATCH.SCRATCH2 Bit Field Locations Address...
  • Page 288 8A3xxxx Family Programming Guide Module: EEPROM Access EEPROM. Table 390: EEPROM Register Index Register Module Base Address: CF68h Offset (Hex) Individual Register Name Register Description 000h EEPROM.EEPROM_I2C_ADDR EEPROM I2C address. 001h EEPROM.EEPROM_SIZE EEPROM data transfer size. 002h EEPROM.EEPROM_OFFSET EEPROM offset. 004h EEPROM.EEPROM_CMD EEPROM command.
  • Page 289 8A3xxxx Family Programming Guide EEPROM.EEPROM_OFFSET Address offset inside the EEPROM. Table 393: EEPROM.EEPROM_OFFSET Bit Field Locations and Descriptions Offset EEPROM.EEPROM_OFFSET Bit Field Locations Address (Hex) 002h EEPROM_OFFSET[7:0] 003h EEPROM_OFFSET[15:8] EEPROM.EEPROM_OFFSET Bit Field Descriptions Bit Field Name Field Type Default Value Description EEPROM_OFFSET[15:0] Unsigned 16-bit value in bytes indicating the offset inside the EEPROM.
  • Page 290 8A3xxxx Family Programming Guide OTP.OTP_CMD Initiate OTP transaction. Table 396: OTP.OTP_CMD Bit Field Locations and Descriptions Offset OTP.OTP_CMD Bit Field Locations Address (Hex) 000h OTP_CMD[7:0] 001h OTP_CMD[15:8] 002h OTP_CMD[23:16] 003h OTP_CMD[31:24] OTP.OTP_CMD Bit Field Descriptions Bit Field Name Field Type Default Value Description OTP_CMD[31:0] OTP.OTP_CM_CTR...
  • Page 291 8A3xxxx Family Programming Guide OTP.OTP_HOST_CTR Word counter updated by the user. Table 398: OTP.OTP_HOST_CTR Bit Field Locations and Descriptions Offset OTP.OTP_HOST_CTR Bit Field Locations Address (Hex) 006h OTP_HOST_CTR[7:0] 007h OTP_HOST_CTR[15:8] OTP.OTP_HOST_CTR Bit Field Descriptions Bit Field Name Field Type Default Value Description OTP_HOST_CTR[15:0] Total number of 32-bit words transferred through the OTP buffer during the...
  • Page 292 8A3xxxx Family Programming Guide Table 399: BYTE Register Index Register Module Base Address: CF80h Offset (Hex) Individual Register Name Register Description 00Fh BYTE.OTP_EEPROM_PWM_BUFF_15 010h BYTE.OTP_EEPROM_PWM_BUFF_16 011h BYTE.OTP_EEPROM_PWM_BUFF_17 012h BYTE.OTP_EEPROM_PWM_BUFF_18 013h BYTE.OTP_EEPROM_PWM_BUFF_19 014h BYTE.OTP_EEPROM_PWM_BUFF_20 015h BYTE.OTP_EEPROM_PWM_BUFF_21 016h BYTE.OTP_EEPROM_PWM_BUFF_22 017h BYTE.OTP_EEPROM_PWM_BUFF_23 018h BYTE.OTP_EEPROM_PWM_BUFF_24 019h BYTE.OTP_EEPROM_PWM_BUFF_25...
  • Page 293 8A3xxxx Family Programming Guide Table 399: BYTE Register Index Register Module Base Address: CF80h Offset (Hex) Individual Register Name Register Description 02Fh BYTE.OTP_EEPROM_PWM_BUFF_47 030h BYTE.OTP_EEPROM_PWM_BUFF_48 031h BYTE.OTP_EEPROM_PWM_BUFF_49 032h BYTE.OTP_EEPROM_PWM_BUFF_50 033h BYTE.OTP_EEPROM_PWM_BUFF_51 034h BYTE.OTP_EEPROM_PWM_BUFF_52 035h BYTE.OTP_EEPROM_PWM_BUFF_53 036h BYTE.OTP_EEPROM_PWM_BUFF_54 037h BYTE.OTP_EEPROM_PWM_BUFF_55 038h BYTE.OTP_EEPROM_PWM_BUFF_56 039h BYTE.OTP_EEPROM_PWM_BUFF_57...
  • Page 294 8A3xxxx Family Programming Guide Table 399: BYTE Register Index Register Module Base Address: CF80h Offset (Hex) Individual Register Name Register Description 04Fh BYTE.OTP_EEPROM_PWM_BUFF_79 050h BYTE.OTP_EEPROM_PWM_BUFF_80 051h BYTE.OTP_EEPROM_PWM_BUFF_81 052h BYTE.OTP_EEPROM_PWM_BUFF_82 053h BYTE.OTP_EEPROM_PWM_BUFF_83 054h BYTE.OTP_EEPROM_PWM_BUFF_84 055h BYTE.OTP_EEPROM_PWM_BUFF_85 056h BYTE.OTP_EEPROM_PWM_BUFF_86 057h BYTE.OTP_EEPROM_PWM_BUFF_87 058h BYTE.OTP_EEPROM_PWM_BUFF_88 059h BYTE.OTP_EEPROM_PWM_BUFF_89...
  • Page 295 8A3xxxx Family Programming Guide Table 399: BYTE Register Index Register Module Base Address: CF80h Offset (Hex) Individual Register Name Register Description 06Fh BYTE.OTP_EEPROM_PWM_BUFF_111 070h BYTE.OTP_EEPROM_PWM_BUFF_112 071h BYTE.OTP_EEPROM_PWM_BUFF_113 072h BYTE.OTP_EEPROM_PWM_BUFF_114 073h BYTE.OTP_EEPROM_PWM_BUFF_115 074h BYTE.OTP_EEPROM_PWM_BUFF_116 075h BYTE.OTP_EEPROM_PWM_BUFF_117 076h BYTE.OTP_EEPROM_PWM_BUFF_118 077h BYTE.OTP_EEPROM_PWM_BUFF_119 078h BYTE.OTP_EEPROM_PWM_BUFF_120 079h BYTE.OTP_EEPROM_PWM_BUFF_121...
  • Page 296 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_1 Table 401: BYTE.OTP_EEPROM_PWM_BUFF_1 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_1 Bit Field Locations Address (Hex) 001h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_1 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_2 Table 402: BYTE.OTP_EEPROM_PWM_BUFF_2 Bit Field Locations and Descriptions Offset...
  • Page 297 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_4 Table 404: BYTE.OTP_EEPROM_PWM_BUFF_4 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_4 Bit Field Locations Address (Hex) 004h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_4 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_5 Table 405: BYTE.OTP_EEPROM_PWM_BUFF_5 Bit Field Locations and Descriptions Offset...
  • Page 298 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_7 Table 407: BYTE.OTP_EEPROM_PWM_BUFF_7 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_7 Bit Field Locations Address (Hex) 007h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_7 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_8 Table 408: BYTE.OTP_EEPROM_PWM_BUFF_8 Bit Field Locations and Descriptions Offset...
  • Page 299 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_10 Table 410: BYTE.OTP_EEPROM_PWM_BUFF_10 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_10 Bit Field Locations Address (Hex) 00Ah DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_10 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_11 Table 411: BYTE.OTP_EEPROM_PWM_BUFF_11 Bit Field Locations and Descriptions Offset...
  • Page 300 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_13 Table 413: BYTE.OTP_EEPROM_PWM_BUFF_13 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_13 Bit Field Locations Address (Hex) 00Dh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_13 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_14 Table 414: BYTE.OTP_EEPROM_PWM_BUFF_14 Bit Field Locations and Descriptions Offset...
  • Page 301 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_16 Table 416: BYTE.OTP_EEPROM_PWM_BUFF_16 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_16 Bit Field Locations Address (Hex) 010h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_16 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_17 Table 417: BYTE.OTP_EEPROM_PWM_BUFF_17 Bit Field Locations and Descriptions Offset...
  • Page 302 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_19 Table 419: BYTE.OTP_EEPROM_PWM_BUFF_19 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_19 Bit Field Locations Address (Hex) 013h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_19 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_20 Table 420: BYTE.OTP_EEPROM_PWM_BUFF_20 Bit Field Locations and Descriptions Offset...
  • Page 303 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_22 Table 422: BYTE.OTP_EEPROM_PWM_BUFF_22 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_22 Bit Field Locations Address (Hex) 016h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_22 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_23 Table 423: BYTE.OTP_EEPROM_PWM_BUFF_23 Bit Field Locations and Descriptions Offset...
  • Page 304 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_25 Table 425: BYTE.OTP_EEPROM_PWM_BUFF_25 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_25 Bit Field Locations Address (Hex) 019h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_25 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_26 Table 426: BYTE.OTP_EEPROM_PWM_BUFF_26 Bit Field Locations and Descriptions Offset...
  • Page 305 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_28 Table 428: BYTE.OTP_EEPROM_PWM_BUFF_28 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_28 Bit Field Locations Address (Hex) 01Ch DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_28 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_29 Table 429: BYTE.OTP_EEPROM_PWM_BUFF_29 Bit Field Locations and Descriptions Offset...
  • Page 306 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_31 Table 431: BYTE.OTP_EEPROM_PWM_BUFF_31 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_31 Bit Field Locations Address (Hex) 01Fh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_31 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_32 Table 432: BYTE.OTP_EEPROM_PWM_BUFF_32 Bit Field Locations and Descriptions Offset...
  • Page 307 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_34 Table 434: BYTE.OTP_EEPROM_PWM_BUFF_34 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_34 Bit Field Locations Address (Hex) 022h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_34 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_35 Table 435: BYTE.OTP_EEPROM_PWM_BUFF_35 Bit Field Locations and Descriptions Offset...
  • Page 308 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_37 Table 437: BYTE.OTP_EEPROM_PWM_BUFF_37 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_37 Bit Field Locations Address (Hex) 025h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_37 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_38 Table 438: BYTE.OTP_EEPROM_PWM_BUFF_38 Bit Field Locations and Descriptions Offset...
  • Page 309 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_40 Table 440: BYTE.OTP_EEPROM_PWM_BUFF_40 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_40 Bit Field Locations Address (Hex) 028h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_40 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_41 Table 441: BYTE.OTP_EEPROM_PWM_BUFF_41 Bit Field Locations and Descriptions Offset...
  • Page 310 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_43 Table 443: BYTE.OTP_EEPROM_PWM_BUFF_43 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_43 Bit Field Locations Address (Hex) 02Bh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_43 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_44 Table 444: BYTE.OTP_EEPROM_PWM_BUFF_44 Bit Field Locations and Descriptions Offset...
  • Page 311 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_46 Table 446: BYTE.OTP_EEPROM_PWM_BUFF_46 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_46 Bit Field Locations Address (Hex) 02Eh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_46 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_47 Table 447: BYTE.OTP_EEPROM_PWM_BUFF_47 Bit Field Locations and Descriptions Offset...
  • Page 312 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_49 Table 449: BYTE.OTP_EEPROM_PWM_BUFF_49 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_49 Bit Field Locations Address (Hex) 031h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_49 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_50 Table 450: BYTE.OTP_EEPROM_PWM_BUFF_50 Bit Field Locations and Descriptions Offset...
  • Page 313 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_52 Table 452: BYTE.OTP_EEPROM_PWM_BUFF_52 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_52 Bit Field Locations Address (Hex) 034h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_52 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_53 Table 453: BYTE.OTP_EEPROM_PWM_BUFF_53 Bit Field Locations and Descriptions Offset...
  • Page 314 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_55 Table 455: BYTE.OTP_EEPROM_PWM_BUFF_55 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_55 Bit Field Locations Address (Hex) 037h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_55 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_56 Table 456: BYTE.OTP_EEPROM_PWM_BUFF_56 Bit Field Locations and Descriptions Offset...
  • Page 315 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_58 Table 458: BYTE.OTP_EEPROM_PWM_BUFF_58 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_58 Bit Field Locations Address (Hex) 03Ah DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_58 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_59 Table 459: BYTE.OTP_EEPROM_PWM_BUFF_59 Bit Field Locations and Descriptions Offset...
  • Page 316 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_61 Table 461: BYTE.OTP_EEPROM_PWM_BUFF_61 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_61 Bit Field Locations Address (Hex) 03Dh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_61 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_62 Table 462: BYTE.OTP_EEPROM_PWM_BUFF_62 Bit Field Locations and Descriptions Offset...
  • Page 317 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_64 Table 464: BYTE.OTP_EEPROM_PWM_BUFF_64 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_64 Bit Field Locations Address (Hex) 040h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_64 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_65 Table 465: BYTE.OTP_EEPROM_PWM_BUFF_65 Bit Field Locations and Descriptions Offset...
  • Page 318 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_67 Table 467: BYTE.OTP_EEPROM_PWM_BUFF_67 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_67 Bit Field Locations Address (Hex) 043h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_67 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_68 Table 468: BYTE.OTP_EEPROM_PWM_BUFF_68 Bit Field Locations and Descriptions Offset...
  • Page 319 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_70 Table 470: BYTE.OTP_EEPROM_PWM_BUFF_70 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_70 Bit Field Locations Address (Hex) 046h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_70 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_71 Table 471: BYTE.OTP_EEPROM_PWM_BUFF_71 Bit Field Locations and Descriptions Offset...
  • Page 320 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_73 Table 473: BYTE.OTP_EEPROM_PWM_BUFF_73 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_73 Bit Field Locations Address (Hex) 049h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_73 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_74 Table 474: BYTE.OTP_EEPROM_PWM_BUFF_74 Bit Field Locations and Descriptions Offset...
  • Page 321 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_76 Table 476: BYTE.OTP_EEPROM_PWM_BUFF_76 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_76 Bit Field Locations Address (Hex) 04Ch DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_76 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_77 Table 477: BYTE.OTP_EEPROM_PWM_BUFF_77 Bit Field Locations and Descriptions Offset...
  • Page 322 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_79 Table 479: BYTE.OTP_EEPROM_PWM_BUFF_79 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_79 Bit Field Locations Address (Hex) 04Fh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_79 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_80 Table 480: BYTE.OTP_EEPROM_PWM_BUFF_80 Bit Field Locations and Descriptions Offset...
  • Page 323 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_82 Table 482: BYTE.OTP_EEPROM_PWM_BUFF_82 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_82 Bit Field Locations Address (Hex) 052h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_82 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_83 Table 483: BYTE.OTP_EEPROM_PWM_BUFF_83 Bit Field Locations and Descriptions Offset...
  • Page 324 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_85 Table 485: BYTE.OTP_EEPROM_PWM_BUFF_85 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_85 Bit Field Locations Address (Hex) 055h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_85 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_86 Table 486: BYTE.OTP_EEPROM_PWM_BUFF_86 Bit Field Locations and Descriptions Offset...
  • Page 325 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_88 Table 488: BYTE.OTP_EEPROM_PWM_BUFF_88 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_88 Bit Field Locations Address (Hex) 058h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_88 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_89 Table 489: BYTE.OTP_EEPROM_PWM_BUFF_89 Bit Field Locations and Descriptions Offset...
  • Page 326 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_91 Table 491: BYTE.OTP_EEPROM_PWM_BUFF_91 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_91 Bit Field Locations Address (Hex) 05Bh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_91 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_92 Table 492: BYTE.OTP_EEPROM_PWM_BUFF_92 Bit Field Locations and Descriptions Offset...
  • Page 327 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_94 Table 494: BYTE.OTP_EEPROM_PWM_BUFF_94 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_94 Bit Field Locations Address (Hex) 05Eh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_94 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_95 Table 495: BYTE.OTP_EEPROM_PWM_BUFF_95 Bit Field Locations and Descriptions Offset...
  • Page 328 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_97 Table 497: BYTE.OTP_EEPROM_PWM_BUFF_97 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_97 Bit Field Locations Address (Hex) 061h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_97 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_98 Table 498: BYTE.OTP_EEPROM_PWM_BUFF_98 Bit Field Locations and Descriptions Offset...
  • Page 329 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_100 Table 500: BYTE.OTP_EEPROM_PWM_BUFF_100 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_100 Bit Field Locations Address (Hex) 064h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_100 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_101 Table 501: BYTE.OTP_EEPROM_PWM_BUFF_101 Bit Field Locations and Descriptions Offset...
  • Page 330 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_103 Table 503: BYTE.OTP_EEPROM_PWM_BUFF_103 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_103 Bit Field Locations Address (Hex) 067h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_103 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_104 Table 504: BYTE.OTP_EEPROM_PWM_BUFF_104 Bit Field Locations and Descriptions Offset...
  • Page 331 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_106 Table 506: BYTE.OTP_EEPROM_PWM_BUFF_106 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_106 Bit Field Locations Address (Hex) 06Ah DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_106 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_107 Table 507: BYTE.OTP_EEPROM_PWM_BUFF_107 Bit Field Locations and Descriptions Offset...
  • Page 332 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_109 Table 509: BYTE.OTP_EEPROM_PWM_BUFF_109 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_109 Bit Field Locations Address (Hex) 06Dh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_109 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_110 Table 510: BYTE.OTP_EEPROM_PWM_BUFF_110 Bit Field Locations and Descriptions Offset...
  • Page 333 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_112 Table 512: BYTE.OTP_EEPROM_PWM_BUFF_112 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_112 Bit Field Locations Address (Hex) 070h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_112 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_113 Table 513: BYTE.OTP_EEPROM_PWM_BUFF_113 Bit Field Locations and Descriptions Offset...
  • Page 334 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_115 Table 515: BYTE.OTP_EEPROM_PWM_BUFF_115 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_115 Bit Field Locations Address (Hex) 073h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_115 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_116 Table 516: BYTE.OTP_EEPROM_PWM_BUFF_116 Bit Field Locations and Descriptions Offset...
  • Page 335 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_118 Table 518: BYTE.OTP_EEPROM_PWM_BUFF_118 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_118 Bit Field Locations Address (Hex) 076h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_118 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_119 Table 519: BYTE.OTP_EEPROM_PWM_BUFF_119 Bit Field Locations and Descriptions Offset...
  • Page 336 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_121 Table 521: BYTE.OTP_EEPROM_PWM_BUFF_121 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_121 Bit Field Locations Address (Hex) 079h DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_121 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_122 Table 522: BYTE.OTP_EEPROM_PWM_BUFF_122 Bit Field Locations and Descriptions Offset...
  • Page 337 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_124 Table 524: BYTE.OTP_EEPROM_PWM_BUFF_124 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_124 Bit Field Locations Address (Hex) 07Ch DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_124 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. BYTE.OTP_EEPROM_PWM_BUFF_125 Table 525: BYTE.OTP_EEPROM_PWM_BUFF_125 Bit Field Locations and Descriptions Offset...
  • Page 338 8A3xxxx Family Programming Guide BYTE.OTP_EEPROM_PWM_BUFF_127 Table 527: BYTE.OTP_EEPROM_PWM_BUFF_127 Bit Field Locations and Descriptions Offset BYTE.OTP_EEPROM_PWM_BUFF_127 Bit Field Locations Address (Hex) 07Fh DATA[7:0] BYTE.OTP_EEPROM_PWM_BUFF_127 Bit Field Descriptions Bit Field Name Field Type Default Value Description DATA[7:0] Data to be transferred into OTP, EEPROM or PWM. ©2018 Integrated Device Technology, Inc September 12, 2018...
  • Page 339 Updated the version numbering to match other documentation. November 2, 2017 First release of this document for the Revision B silicon. Updated to match v4.0.0 / v4.0.1 (Pipeline 7017) and Timing Commander Personality v3.x ©2018 Integrated Device Technology, Inc September 12, 2018 IDT CONFIDENTIAL...
  • Page 340 IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea- sonably expected to significantly affect the health or safety of users.

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