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7.3.2 Test of the clocksignals
Measurement method
These measurements have to be carried out just after
hardware reset. This is done each time after opening the lid
or after power-on.
Use a FET-probe to minimalise the oscillator-loads.
System clock
30.2098 MHz± 20 ppm (NTSC)
30.0000 MHz± 50 ppm (PAL)
This system clock must be present at the following points:
IC 721
o
on pin 30
IC 7125 on pin 115
IC 7302 on pin 1
At IC 7210 pin 29 the Clock divided by two must be present:
15.0000 MHz± 50 ppm (PAL)
15.1049 MHz ± 20 ppm (NTSC)
At IC 7210 pin 69 the UART-clock must be present:
4.9152 MHz ± 50 ppm
At IC 7201 the clock of the 68HC05I8 must be present:
4.000 MHz ± 55 ppm
At connector 1096 on pin C3 the XT2N-clock must be
present:
15.1049 MHz ± 20 ppm (NTSC)
15.0000 MHz± 50 ppm (PAL)
At IC 7310 on pin 22 the CIAP-clock must be present:
33.8688 MHz± 50 ppm
At IC 7401 on pin 19 the DSIC2-clock must be present:
8.4672 MHz ± 50 ppm
At IC 7510 on pin 13 the AUDIO_CLK-clock must be
present:
16.9344 MHz
±
50 ppm
PCS 72 142
7.3.3 Test of the 12S Interface
SDATA IC 7510, pin 21 : block wave signal
SWCLK IC 7510, pin 22 : 44.1 kHz (CODA)
SCLK IC 7510, pin 23: 2.8224 MHz (CODA)
7.3.4 Test of the microcontroller 68070
Check after power on and RESET
=
+5V.
HAL TN IC 7210, pin 27 : +5V
RESETN IC 7210, pin 28 : +5V
DTACKN IC 7210, pin 24: changing +5V/0V
BERAN IC 7210, pin 26 : +5V
7.3.5 Test of the hardware with the Low Level Test
This test makes it possible to test the hardware with
software.
Connect a terminal to the UART of the microcontroller
68070 via connector 1032.
Settings of the terminal:
Baudrate : 9600
start bit : 1
data bits: 8
stop bits: 0
no parity/no handshake
To start the low level test, hit the space bar while putting the
power on.
To test the PCB you only have to follow the instructions on
the screen.
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