M12L64164A Ic Specification - Philips HTS5110 Service Manual

M12L64164A IC Specification

SDRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6 μ s refresh interval
GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
V
DD
DQ 0
V
D D Q
DQ 1
DQ 2
V
S S Q
DQ 3
DQ 4
V
D D Q
DQ 5
DQ 6
V
S S Q
DQ 7
V
DD
L DQ M
W E
C AS
R AS
CS
A
13
A
12
A /AP
10
A
A
A
A
V
DD
1M x 16 Bit x 4 Banks
Synchronous DRAM
ORDERING INFORMATION
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE Comments
M12L64164A-5TG 200MHz TSOP II
M12L64164A-6TG 166MHz TSOP II
M12L64164A-7TG 143MHz TSOP II
Top View
54 V
1
SS
2 53 DQ15
3 52 V
S S Q
4 51 DQ14
50 DQ13
5
6 49 V
D D Q
7 48 DQ12
8 47 DQ11
46
9 V
S S Q
45 DQ10
10
11 44 DQ 9
12 43 V
D D Q
13 42 DQ 8
41 V
14
S S
15 40 N C
16 39 U D Q M
17 38 CLK
37
18 CKE
36 N C
19
20 35 A
11
21 34 A
9
22 33 A
8
32 A
23
0 7
24 31 A
1 6
25 30 A
2 5
26 29 A
4
3
28
27 V
S S
15-4
FUNCTIONAL BLOCK DIAGRAM
CLK
Clock
Generator
CKE
Address
Mode
Register
Pb-free
CS
Pb-free
RAS
Pb-free
CAS
WE
PIN FUNCTION DESCRIPTION
P N I N A M
CLK System Clock
Chip Select
CS
CKE Clock Enable
A0 ~ A11 Address
A12 , A13 Bank Select Address
Row Address Strobe
RAS
Column Address Strobe
CAS
Write Enable
WE
L(U)DQM Data Input / Output Mask
DQ0 ~ DQ15 Data Input / Output
VDD / VSS Power Supply / Ground
VDDQ / VSSQ Data Output Power / Ground
NC No Connection
Bank D
Bank C
Bank B
Row
Address
Buffer
Bank A
&
Refresh
Counter
Sense Amplifier
Column
Column Decoder
Address
Buffer
&
Refresh
Counter
Data Control Circuit
E N I P U T F U N C
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, t after the clock and masks the output.
SHZ
Blocks data input when L(U)DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
15-4
L(U)DQM
DQ
I T O N