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Circuit Description
L-
5. VERTICAL
OUTPUT
An IC (LA7832) is used for the vertical output circuit in this
chassis.
The vertical
drive pulse from pin43 of ICI 01 is
input to pin4 of IC451.
This
pulse
drives
IC451,
and
vertical scanning
is performed.
In the first half of scanning
,
a deflecting
current
is output
from
pin2
and
passes
through the following path:
*
VCC(B4) +
D451 +
pin3 @ pin2 +
DY +
C461 @
VR451 /R459.
An electric charge is then stored in C461. In the last half of
scanning the current path is:
C461 + DY + pin2 @ pinl +VR451/R459
+ C461
In this way,
an amplifying
sawtooth
waveform
current
flows directly to DY to perform electron
beam deflection.
L
Next, in the first half of the blanking
period the vertical
drive
pulse
suddenly
becomes
OFF,
and in order
to
reduce
the
current
flowing
to
DY,
the
current
path
becomes as follows by the inductance
of DY:
DY+pin2+
pinl +VR451/R459+C461
+ DY
Also, when the charge of DY has dissipated,
the current
path becomes:
Vcc+
pin6+
pin7+
C452+
pin3+
pin2+
DY+C461
+
vR451/R459
and when the prescribed
current
value
is reached,
the
vertical
drive pulse
becomes
ON. This completes
one
cycle.
6. HORIZONTAL
OUTPUT
L
A horizontal
oscillation
signal
is output
from
pin37
of
IC101
and
switches
the
drive
transistor
Q431.
This
switching
signal
is
current
amplified
by
the
drive
transformer
T431 and drives the output transistor
Q432.
When
Q432
becomes
ON, an amplifying
current
flows
directly to DY through
;
C441 /C442 + L441 /R441 + DY + Q432- C + Q432-
E
and deflection
is performed
in the last half of the scanning
c
period. Next, when Q432 becomes
OFF, the charge that
had
been
stored
in DY up to that
point
releases
a
resonance
current to the resonant
capacitors
C435 and
C436 and charges them. The current stored in C435 and
C436 is then flowed back to DY, and an opposite charge
is then stored in DY. This opposite
charge then switches
the dumper
diode
in Q432 ON, the resonance
state is
L
completed,
and an amplifying
current is then flowed again
directly to DY through the dumper diode.
By this means, deflection
in the first half of the scanning
period is performed
, and when Q432 becomes ON at the
end of the first half of the scanning
period,
deflection
during the last half is begun, thus completing
one cycle.
7. SYSTEM
SWITCHING
(For multi- standard model)
The
system
switches
(S1 -
S11 ) are used for multi -
standard model.
(Refer to Block Diagram of system switching circuit)
S1 :Switch for band-limiting
on NTSC(3.58)
mode (Dl 06)
This
switch
is driven
by ON/OFF
signal
of CPU
(pin40).
S2:Switch
for sound
carrier
trap on NTSC(3.58)
mode
(D120)
This switch is driven by signal of CPU (pin40) too.
S3:Switch
for sound carrier trap except NTSC(3.58)
mode
(D121)
This
switch
is driven
by inverting
signal
of CPU
(pin40).
S4:System
switch for forced SECAM mode (Q203)
This
switch
is driven
by ON/OFF
signal
of CPU
(pin44).
S5:lnput switch for SECAM colour demodulation
(IC290)
This
switch
is driven
by ON/OFF
signal
of CPU
(pin41).
S6:System
switch for forced 4.43 mode (Q222)
This
switch
is driven
by ON/OFF
signal
of CPU
(pin43).
Note: When the colour system is set to "AUTO,
both S6
and S7 will turn on.
S7:System
switch for forced 3.58 mode (Q221 )
This
switch
is
(pin42).
S8:System
switch
mode (Ql 53)
This
switch
is
(pin40).
S9:System
switch
(QI 54)
This
switch
is
(pin39).
driven
by ON/OFF
for 4.5 MHz filtering
driven
by ON/OFF
for
5.5 MHz
filtering
driven
by ON/OFF
SIO:System
switch for 6.0 MHz filtering on
This
switch
is driven
by ON/OFF
(pin38).
signal
of CPU
on NTSC(3.58)
signal
of CPU
on
B/G
mode
signal
of CPU
I mode (Ql 55)
signal
of CPU
S11
:System
switch
for 6.5MHz
filtering
on D/K mode
(QI 56)
This
switch
is driven
by ON/OFF
signal
of CPU
(pin37).
Note:
When the TV system is set to "AUTO", S8, S9, S1 O
and S11 will turn on.
–5–
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