Marantz DV9500 Service Manual page 119

Pin No. Mnemonic
11, 57 DGND
40 AGND
32 CLKIN_A
63 CLKIN_B
36, 45 COMP2, COMP1
44 DAC A
43 DAC B
42 DAC C
39 DAC D
38 DAC E
37 DAC F
23 P_HSYNC
24 P_VSYNC
25 P_BLANK
48 S_BLANK
50 S_HSYNC
49 S_VSYNC
2–9, 12–13 Y9–Y0
14–18, 26–30 C9–C0
51–55, 58–62 S9–S0
33 RESET
, R
35, 47 R
SET2 SET1
22 SCLK
21 SDA
20 ALSB
1 V
DD_IO
10, 56 V
DD
41 V
AA
46 V
REF
34 EXT_LF
31 RTC_SCR_TR
2
19 I C
64 GND_IO
PIN FUNCTION DESCRIPTIONS
Input/Output Function
G D igital Ground.
G Analog Ground.
I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only
(27 MHz).
I Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This
clock is only used in dual modes.
O Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin
to V .
AA
O CVBS/Green/Y/Y Analog Output.
O Chroma/Blue/U/Pb Analog Output.
O Luma/Red/V/Pr Analog Output.
O In SD Only Mode: CVBS/Green/Y Analog Output.
In HD Only mode and simultaneous HD/SD mode: Y/ Green [HD] Analog
Output.
O In SD Only Mode: Luma/ Blue/U Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pr/ Red Analog Output.
O In SD Only Mode: Chroma/ Red/V Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pb/ Blue [HD] Analog
Output.
I V ideo Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.
I V ideo Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.
I Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD.
I/O Video Blanking Control Signal for SD only.
I/O Video Horizontal Sync Control Signal for SD Only.
I/O Video Vertical Sync Control Signal for SD Only.
I SD or Progressive Scan/HDTV Input Port for Y Data. Input port for inter-
leaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data
input, LSB is set up on Y2.
I Progressive Scan/HDTV Input Port. In 4:4:4 Input mode, this port is used for
the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB
is set up on C2.
I SD or Progressive Scan/HDTV Input Port for Cr [Red/V] Data in 4:4:4 Input
Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2.
I T his input resets the on-chip timing generator and sets the ADV7314 into
default register setting. RESET is an active low signal.
I A 3040
to control the amplitudes of the DAC outputs.
2
I I C Port Serial Interface Clock Input.
2
I/O I C Port Serial Data Input/Output.
I TTL Address Input. This signal sets up the LSB of the I
this pin is tied low, the I
interface.
P Power Supply for Digital Inputs and Outputs.
P Digital Power Supply.
P Analog Power Supply.
I/O Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V).
I External Loop Filter for the Internal PLL.
I M ultifunctional Input. Real-time control (RTC) input, timing reset input,
subcarrier reset input.
I This input pin must be tied high (V
over the I
Digital Input/Output Ground.
resistor must be connected from this pin to AGND and is used
2
C filter is activated, reducing noise on the I
2
C port.
117
2
C address. When
) for the ADV7314 to interface
DD_IO
2
C