Yamaha RP-U200 Service Manual page 26

RP-U200
IC475 : LC27287B-TF3
Embedded Array
No. Name I/O
1 VSS I
2 XI I
3 XO O
4 /SIOIRQ O
5 /FIFOIRQ O
6 A0 I
7 A1 I
8 A2 I
9 A3 I
10 A4 I
11 A5 I
12 TEST9 I
13 TEST10 I
14 D0 I/O
15 D1 I/O
16 D2 I/O
17 D3 I/O
18 D4 I/O
19 D5 I/O
20 D6 I/O
21 D7 I/O
22 VDD5 I
23 VSS I
24 D8 I/O
25 D9 I/O
26 D10 I/O
27 D11 I/O
28 D12 I/O
29 D13 I/O
30 D14 I/O
31 D15 I/O
32 RDB I
33 WRL I
34 WRH I
35 GACS I
36 GARST I
37 CPUCLK I
38 DMVDD I
39 USBDACO O
40 CAPTIN I
41 TEST0 I
42 TEST1 I
43 TEST2 I
44 VDD5 I
45 VSS I
46 MCLKAI I
47 MCLKAO O
48 PIO0 O
49 PIO1 I
50 PIO2 I
51 PIO3 I
52 PIO4 I
53 PIO5 I
54 PIO6 I
55 PIO7 I
25
Function
GND
X'tal in (GND)
X'tal out (OPEN)
Serial IRQ (OPEN)
FIFO IRQ (/EAINT)
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
(OPEN)
(OPEN)
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
+5V
GND
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Read Strobe input
Write Strobe Low input
Write Strobe High input
Bus Chip Select (EACS)
Global Reset input (USBRST)
System clock input
Master Vdd active detection
USB audio data
USB capture audio data in (PAO7)
OPEN
OPEN
OPEN
+5V
GND
X'tal in (11.2896MHz)
X'tal out (11.2896MHz)
TUNER MUTE
TUNER TUNED
TUNER STEREO
YSS928 AC3DATA
YSS928 SURENC
YSS928 DIRERR
YSS928 DIRLOCK
YSS928 KARAOKE
No. Name I/O Function
56 PIO8 I YSS928 OVFB
57 PIO9 I YSS928 DTSDATA
58 PIO10 I YSS928 ZEROFLOG
59 PIO11 I YSS928 CRC
60 PIO12 O 48/96
61 PIO13 I YSS928 DBL/V
62 PIO14 O ANSEL
63 PIO15 I/O Extended I/O port (OPEN)
64 I2CCK O I2C serial Bus clock (OPEN)
65 I2SDA I/O I2C serial Bus data (OPEN)
66 VDD5 I +5V
67 VSS I GND
68 MCLKBI I X'tal in (GND)
69 MCLKBO O X'tal out (OPEN)
70 TEST3 I (OPEN)
71 TEST4 I (OPEN)
72 TEST5 I (OPEN)
73 TEST6 I H: PLL TEST out, L: normal (OPEN)
74 TEST7 I H: pllclks in, L: NC (OPEN)
75 TEST8 I H: PLL TEST out, L: normal (OPEN)
76 PLLCKO I PLL clock input
77 PLLREF O PLL reference clock out
78 RFCLK I Internal PLL reference clock
79 VDD33 I +3.3V
80 PCH O PLL PCH out (TEST8: H) (OPEN)
81 NCH O PLL NCH out (TEST8: H) (OPEN)
82 DIV2 O Internal PLL VCO div2 (OPEN)
83 VSS I GND
84 PO O Charge pump out
85 VCNT I VCO control input
86 R I VCO Bias Resistor
87 AVSS I GND (for Analog)
88 AVDD I +3.3V (for Analog)
89 VSS I GND
90 VDD5 I +5V
91 SFS O Other device audio clock
92 /S64FS O Other device audio clock
93 S128FS O Other device audio clock (OPEN)
94 S256FS O Other device audio clock
95 SSYNC O Other device audio clock (OPEN)
96 R64FS O Render device bit clock (OPEN)
97 C64FS O Capture device bit clock (OPEN)
98 D64FS O USB bit clock (OPEN)
99 S64FS O Other device bit clock (OPEN)
100 X64FS O External bit clock (DIR) (OPEN)
101 XFS I External audio clock (DIR)
102 /X64FS I External audio clock (DIR)
103 X128FS I External audio clock (DIR)
104 X256FS I External audio clock (DIR)
105 XSYNC I External audio clock (DIR)
106 PAI3 I Patch input (A/D)
107 PAI4 I Patch input (YSS928 SDOB0)
108 PAI5 I Patch input (YSS928 SDOB1)
109 PAI6 I Patch input (YSS928 SDOB2)
110 VDD33 I +3.3V