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Pin No.
Terminal
106
EOEB
108
VCC7
111
ECEB
113 ~ 117
ED11 ~ ED15
118
VCC4
119
GND4
120 ~ 122
ED8 ~ ED10
123 ~ 130
ED0 ~ ED7
131
GND6
132 ~ 134
—
135, 136
—
Block diagram of DSP and DAC circuit
D0 ~ D7
From CPU
A0 ~ A3
Gate Array
LSI17
UPD65611GB
I n / O u t
Out
In
Out
—
In
In
—
In/Out
In
—
—
Sound Source ROM
LSI12
MX23C2410MC-12CA54
CE
A0 ~ A20
RA0 ~
RA22
RA20
DSP
LSI11
RESET
RESB
LSIB
CRDB
HG51B155FD-1
RDAB
CCSB
WRAB
CWRB
ECEB EOEB EWEB
WE
OE
CS
Effect RAM (256K-bit)
LC33832M-70-TLM
— 9 —
Function
Read enable signal output for the effect RAM
+5 V source
Chip select signal output for the effect RAM
Not used
+5 V source
Ground (0 V) source
Not used
Data bus for the effect RAM
Ground (0 V) source
Not used. Connected to ground.
Not used
Q0 ~ Q15
RD0 ~
RD15
SOLP
BOK
WOK1
EA0 ~
ED0 ~
ED7
EA14
I/01 ~ I/08 A0 ~ A14
LSI13
SOLP: Sound data
BOK: Bit clock
WOK1: Word clock
DAC
IC11
ROUT
SI
CLK
LOUT
LRCK
UPD6376GS
PG
X11
24.576 MHz
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