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EN 36
8.
3139 785 34110
PIN CONFIGURATION
DOUT
SG1/KS1
SG2/KS2
SG3/KS3
SG4/KS4
SG5/KS5
SG6/KS6
Pin Name
O
S
C
DOUT
D
N I
C
L
K
S
T
B
K1 ~ K3
V
D
D
SG1/KS1 ~ SG10/KS10
N
C
S
G
1
1
S
G
1
/ 2
G
R
7
GR6 ~ GR1
G
N
D
IC Description
OSC
1
2
DIN
3
CLK
4
STB
5
K1
6
K2
7
K3
8
PT6961
VDD
9
10
11
12
NC
13
14
15
16
I/O
Oscillator Input Pin
I
A resistor is connected to this pin to determine the
oscillation frequency
Data Output Pin (N-Channel, Open-Drain)
O
This pin outputs serial data at the falling edge of the
shift clock.
Data Input Pin
I
This pin inputs serial data at the rising edge of the
shift clock (starting from the lower bit)
Clock Input Pin
I
This pin reads serial data at the rising edge and
outputs data at the falling edge.
Serial Interface Strobe Pin
The data input after the STB has fallen is processed
I
as a command. When this pin is HIGH", CLK is
ignored.
Key Data Input Pins
I
The data sent to these pins are latched at the end
of the display cycle. (Internal Pull-Low Resistor)
-
P
o
w
r e
S
u
p
Segment Output Pins (p-channel, open drain)
O
Also acts as the Key Source
-
N
o
C
o
n
n
e
t c
O
S
e
g
m
e
t n
O
O
S
e
g
m
e
n
/ t
G
O
Grid Output Pins
-
G
o r
u
n
d
P
n i
32
GND
31
GR1
30
GR2
29
GND
28
GR3
27
GR4
26
GND
25
VDD
24
GR5
23
GR6
22
SG12/GR7
21
SG11
20
SG10/KS10
19
SG9/KS9
18
SG8/KS8
17
SG7/KS7
Figure 8-2
Description
p
y l
o i
n
u
p t
t u
p
n i
s
(
- P
C
h
a
n
n
e
, l
r
d i
O
u
p t
t u
P
n i
s
Pin No.
6, 7, 8
10 ~ 12,
14 ~ 20
o
p
e
n
r d
i a
) n
23, 24, 27,
28, 30, 31
2
, 6
1
2
3
4
5
, 9
2
5
1
3
2
1
2
2
2
, 9
3
2
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