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The Embedded I/O Company
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7
25469 Halstenbek, Germany
www.tews.com
TCP201
Compact PCI IP Carrier
Version 1.0
User Manual
Issue 1.4
September 2006
Phone: +49-(0)4101-4058-0
Fax: +49-(0)4101-4058-19
e-mail: info@tews.com
TEWS TECHNOLOGIES LLC
9190 Double Diamond Parkway,
Suite 127, Reno, NV 89521, USA
www.tews.com
Phone: +1 (775) 850 5830
Fax: +1 (775) 201 0347
e-mail: usasales@tews.com
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Table of Contents
Related Manuals for Tews Technologies TCP201
Summary of Contents for Tews Technologies TCP201
- Page 1 The Embedded I/O Company TCP201 Compact PCI IP Carrier Version 1.0 User Manual Issue 1.4 September 2006 TEWS TECHNOLOGIES GmbH TEWS TECHNOLOGIES LLC Am Bahnhof 7 Phone: +49-(0)4101-4058-0 9190 Double Diamond Parkway, Phone: +1 (775) 850 5830 25469 Halstenbek, Germany...
- Page 2 However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice. TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or use of the device described herein.
- Page 3 Initial Issue October 2002 Corrections in Chapter Endian Conventions November 2002 General Revision March 2003 Correction Figure “ PCI to Local Byte lane swapping” November 2003 New address TEWS LLC September 2006 TCP201 User Manual Issue 1.4 Page 3 of 35...
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Page 4: Table Of Contents
Intel CPU View........................16 3.4.2 PowerPC CPU View ......................17 3.4.3 Intel CPU View with TCP201 switched to Big Endian ............18 3.4.4 PowerPC CPU View with TCP201 switched to Big Endian..........19 3.5 Big / Little Endian Mode setting ....................20 IP INTERFACE ......................21 4.1 PCI9030 Local Space Assignment ....................21... - Page 5 FIGURE 3-5 : POWERPC CPU VIEW ......................17 FIGURE 3-6 : INTEL CPU VIEW WITH TCP201 SWITCHED TO BIG ENDIAN..........18 FIGURE 3-7 : POWERPC CPU VIEW WITH TCP201 SWITCHED TO BIG ENDIAN ........19 FIGURE 3-8 : PCI TO LOCAL BYTE LANE SWAPPING ................20 FIGURE 4-1 : PCI9030 LOCAL SPACE ASSIGNMENT.................21...
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Page 6: Product Description
For improved EMI protection, four HD50 SCSI-2 type connectors (AMP 787395-5) are mounted in the EMI front panel of the TCP201 and provide access to all IP I/O lines. Status indicators for IP access, +5V and +/-12V are provided in the front panel. -
Page 7: Technical Specification
– 40°C to + 85°C Storage – 40°C to + 85°C 170766 h MTBF Weight 310g Size 160mm x 233.35mm Humidity 5 – 95 % non-condensing Figure 2-1 : Technical Specification TCP201 User Manual Issue 1.4 Page 7 of 35... -
Page 8: Pci Interface
3 PCI Interface The TCP201 is accessible in the PCI Memory space. The PCI9030 PCI Target Chip from PLX Technology is used as PCI target device for accessing the IP interface. A FPGA is used on the PCI9030 local bus to build the IP interface and provide IP interface control registers. -
Page 9: Pci Configuration (Cfg) Registers
Capability ID Y[23:16] 00 02 4C 06 Pointer 0x4C VPD Address Next_Cap Capability ID Y[31:16] 0000 00 03 Pointer 0x50 VPD Data Register 00000000 Figure 3-1 : PCI Configuration Register Map TCP201 User Manual Issue 1.4 Page 9 of 35... -
Page 10: Pci Base Address Initialization
PCI address space by programming the PCI Base Address Register. After programming the required address spaces the user must set bit 0 (enables I/O accesses) and bit 1 (enables memory accesses) of the Command Register (Offset 0x04) to ‘1’. TCP201 User Manual Issue 1.4 Page 10 of 35... -
Page 11: I/O Base Address Implementation
In addition, it must comply with the definition contained in bits 1 and 2 of this register. The PCI Base Address 0 for Memory Mapped Configuration Registers (128 byte) and the PCI Base Addresses 2 to 5 for Local Address Space 0 to 3 are used by the TCP201 as memory address space. -
Page 12: Expansion Rom Base Address Implementation
Expansion ROM Register. This memory address region must not conflict with any other memory space utilized within the system. The Expansion ROM is not used by the TCP201. For further information please refer to the PCI9030 manual which is also part of the TCP201-ED Engineering Documentation. TCP201 User Manual Issue 1.4... -
Page 13: Local Configuration Register
General Purpose I/O Control 0x02249252 GPI/O2=CS2# GPI/O3=CS3# 0x70 Hidden 1 Power Management data select 0x00000000 Not used 0x74 Hidden 2 Power Management data scale 0x00000000 Not used Figure 3-2 : Local Configuration Registers TCP201 User Manual Issue 1.4 Page 13 of 35... -
Page 14: Target Configuration Eeprom
0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xE0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xF0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF Figure 3-3 : PCI9030 Configuration EEPROM Content TCP201 User Manual Issue 1.4 Page 14 of 35... -
Page 15: Endian Conventions
Big Endian mode. Most IP modules, which are common in VMEbus systems, also use Big Endian byte ordering. The TCP201 works in Little Endian mode by default, but can be switched to work in Big Endian mode. This leads to 4 major Big- Little Endian combinations in one system:... -
Page 16: Intel Cpu View
3.4.1 Intel CPU View Figure 3-4 : Intel CPU View TCP201 User Manual Issue 1.4 Page 16 of 35... -
Page 17: Powerpc Cpu View
3.4.2 PowerPC CPU View Figure 3-5 : PowerPC CPU View TCP201 User Manual Issue 1.4 Page 17 of 35... -
Page 18: Intel Cpu View With Tcp201 Switched To Big Endian
3.4.3 Intel CPU View with TCP201 switched to Big Endian Figure 3-6 : Intel CPU View with TCP201 switched to Big Endian TCP201 User Manual Issue 1.4 Page 18 of 35... -
Page 19: Powerpc Cpu View With Tcp201 Switched To Big Endian
3.4.4 PowerPC CPU View with TCP201 switched to Big Endian Figure 3-7 : PowerPC CPU View with TCP201 switched to Big Endian TCP201 User Manual Issue 1.4 Page 19 of 35... -
Page 20: Big / Little Endian Mode Setting
3.5 Big / Little Endian Mode setting The PCI target chip of the TCP201, the PCI9030 can be set to convert to Big Endian data ordering on the local bus. This is useful for IP modules that use Big Endian byte ordering. Big Endian byte ordering is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention. -
Page 21: Ip Interface
The IP FPGA also provides the IP Interface Control Registers. A PCI access to the TCP201 will be terminated in every case. If the IP does not generate an ACK#, a local timeout will terminate the IP access after a timeout time of 8µs and the timeout bit is set in the IP Status Register. -
Page 22: Local Space 0 Address Map
0x0000_037F IP D I/O Space 0x0000_0380 0x0000_03BF IP D ID Space 0x0000_03C0 0x0000_03FF IP D INT Space Figure 4-3 : Local Space 1 Address Map (IP A-D ID, INT, I/O Space) TCP201 User Manual Issue 1.4 Page 22 of 35... -
Page 23: Local Space 2 Address Map
The TCP201 supports read and write cycles to the IP I/O space. The TCP201 supports read and write cycles to the IP ID space. A PCI access to the TCP201 will be terminated in every case. If the IP supports write access to its ID space, data will be written to the ID- PROM. -
Page 24: Local Space 3 Address Map
Description (MSB) Read: Always 0 Write: No Effect REV_ID Read: FPGA Logic Revision ID Write: No Effect 0 (LSB) Figure 4-6 : Revision ID Register (PCI Base Address 2 + 0x00) TCP201 User Manual Issue 1.4 Page 24 of 35... -
Page 25: Ip Control Register
The status of the IP ERROR# line can be read from the IP Status Register. If the TIME_INT_EN bit is set to “1” and an IP timeout occurs, the TCP201 will generate an interrupt. This interrupt can be cleared by writing ‘1’ to the corresponding IP timeout status bit in the IP Status Register. -
Page 26: Figure 4-8 : Ip B Control Register (Pci Base Address 2 + 0X04)
0 (LSB) CLKRATE 0 : IP B clock Rate 8 MHz 1 : IP B clock Rate 32 MHz Figure 4-8 : IP B Control Register (PCI Base Address 2 + 0x04) TCP201 User Manual Issue 1.4 Page 26 of 35... -
Page 27: Figure 4-9 : Ip C Control Register (Pci Base Address 2 +0X06)
0 (LSB) CLKRATE 0 : IP C clock rate 8 MHz 1 : IP C clock rate 32 MHz Figure 4-9 : IP C Control Register (PCI Base Address 2 +0x06) TCP201 User Manual Issue 1.4 Page 27 of 35... -
Page 28: Figure 4-10: Ip D Control Register (Pci Base Address 2 + 0X08)
0 (LSB) CLKRATE 0 : IP D clock rate 8 MHz 1 : IP D clock rate 32 MHz Figure 4-10: IP D Control Register (PCI Base Address 2 + 0x08) TCP201 User Manual Issue 1.4 Page 28 of 35... -
Page 29: Ip Reset Register
Interrupt status of all IP interrupt lines can read in the IP Status Register. If edge sensitive interrupt is enabled (see IP Control Register for detail) and an interrupt is active, writing a “1” to bit 7:0 clears the corresponding interrupt status. TCP201 User Manual Issue 1.4 Page 29 of 35... - Page 30 Read : 0 : No IP_C interrupt 1 request 1 : Active IP_C interrupt 1 request Write : 0 : No effect 1 : Clear edge sensitive IP_C interrupt 1 status TCP201 User Manual Issue 1.4 Page 30 of 35...
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Page 31: Ip Interrupts
Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register. IP Error interrupts must be cleared in the corresponding IP Control Register. TCP201 User Manual Issue 1.4 Page 31 of 35... -
Page 32: Ip Strobe Signal
IP module. It is reserved for a digital strobe or clock signal related to the functionality of the IP. Strobe signals of all IP slots are accessible on the TCP201 via a 4-pin jumper field. Figure 5-1 : IP Strobe Signal TCP201 User Manual Issue 1.4... -
Page 33: Installation Of Industrypacks
After an IP has been installed it can be secured on the carrier board. This is normally necessary only in high vibration or shock environments. Screws and spacers are required to fix a single IP on the TCP201. They can be ordered from TEWS TECHNOLOGIES (Part number: TIPxxx-HK). -
Page 34: Indicators
Figure 7-2 : IP Power LED 7.2 Fuses and Filters All IP slots are fuse protected. The fuses used on the TCP201 are self-healing fuses. For improved performance the TCP201 provides RF filtering and decoupling capacitors on all IP power lines. -
Page 35: Pin Assignment
8 Pin Assignment 8.1 IP Connectors The table below shows the complete IP J1 logic interface pin assignments. Some of these signals are not used on the TCP201. Pin # Signal Pin # Signal Pin # Signal Pin # Signal...
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