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LSI L64005 Technical Manual

Enhanced mpeg-2 audio/video decoder
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L64005
Enhanced MPEG-2
Audio/Video Decoder
Technical Manual
Final Edition May 1998

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  • Page 1 L64005 Enhanced MPEG-2 Audio/Video Decoder Technical Manual Final Edition May 1998...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
  • Page 3 Preface This book is the primary reference and technical manual for the L64005 MPEG-2 Audio/Video Decoder. It contains a complete functional descrip- tion and includes complete physical and electrical specifications for the L64005. Audience This document assumes that you have some familiarity with microproces- sors and related support devices.
  • Page 4 first time a word or phrase is defined in this manual, it is italicized. The following signal naming conventions are used throughout this manual: Preface Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 5 (for pin 69) allows switching between the loop fil- ter and the CAS signal. Pinout Changes If the L64005 is used with fast page mode DRAM, then a few changes are needed. For further information, please refer to Chapter 9: Specifica- tions.
  • Page 6 512-page size select. In the L64005, bits [4:3] are used to select the DRAM mode. Refer to Chapter 2 for more details. ♦ In the L64005 32-bit mode is not supported. Bit 5 of Group 7, Reg- ister 1 is now reserved. ♦...
  • Page 7 Field First and Last Active Field have been added to Group 6, Reg- ister 31, Bits [3:2]. Refer to Section 2.8.18, “Group 6 Display Mode 1” for more details. L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 8 Preface Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.

  • Page 9: Table Of Contents

    1-20 1.6.2 System Layer Decoding 1-21 1.6.3 Video Output Features 1-21 1.6.4 On-Screen Display 1-24 1.6.5 Audio Decoder 1-24 L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 10 2-30 2.8.15 Group 6 OSD Field 1 Pointer 2-31 2.8.16 Group 6 OSD Field 2 Pointer 2-32 2.8.17 Group 6 Display Mode 0 2-32 Contents Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 11 Group 7 Pan and Scan Control 2-58 2.9.19 Group 7 Reduced Memory Mode Control 2-59 2.9.20 Group 7 Reserved Registers 2-60 L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 12 Post-Parser Operation Channel Buffer Operation 4-10 4.3.1 Channel Buffer Hardware 4-10 4.3.2 User Data Buffer 4-11 4.3.3 Auxiliary Data Buffer 4-12 Elementary Stream Decoding 4-13 Contents Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 13 Display Control Parameters 6-11 6.5.1 Video Raster Timing (Master Mode 6-12 6.5.2 VCode Delay 6-17 6.5.3 Slave Mode 6-17 L64005 MPEG-2 Audio/Video Decoder Technical Manual xiii Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 14 Determining the Presentation Time 7.2.6 Ancillary Channel Data 7.2.7 Error Detection 7.2.8 Output Control Chapter 8 System Stream Decoding and Synchronization System Parser Basics Contents Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 15 Engineering Practice for Mixed Voltage Systems 9.4.6 Precautions During Power Sequencing 9.4.7 Precautions to Avoid Bus Contention 9.4.8 Precautions During Power Failure L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 16 The Single Word Write Routine Multiple Word Write Routine Single Word Read Routine Multiple Word Read Routine Regular DRAM Read and Write Timing 5-12 Contents Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 17 PTS Association with Presentation Unit 8-24 8.13 Picture Type Routine 8-25 8.14 Audio PTS Association 8-27 8.15 Audio Sync Algorithm 8-28 L64005 MPEG-2 Audio/Video Decoder Technical Manual xvii Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 18 Word Accesses Vs. 81MHz Clock Cycle in SDRAM Mode 5-14 Channel Buffer Architecture 5-20 Post-processing modes Chroma Line Repeat: Coefficients for Odd and Even Fields xviii Contents Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 19 DC Logic Levels A.12 DC Characteristics A.13 ibuf (3.3V Input), LVTTL AC Characteristics A.14 ibuff, LVTTL Input Buffer, Non-inverting, 5V-Compatible L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.
  • Page 20 A.15 DC Characteristics without Resistor Load A.16 3-State Output Buffer, 5 V-Compatible AC Characteristics Contents Final Rev F Copyright © 1996, 1997, 1998 by LSI Logic Corporation. All rights reserved.

  • Page 21: Introduction

    Moving Picture Expert’s Group MPEG-2 International Standard (IS) 13818 as applied to video compression and decompression. These sec- tions provide a good foundation for the L64005-specific discussion that follows in Sections 1.5 through 1.7. The MPEG standard defines a format for compressed digital video.

  • Page 22: Video Encoding

    Resolutions are about 352 pixels horizontally up to about 288 lines vertically for MPEG-1 and 720 x 576 for MPEG-2 (main profile/main level). The L64005 is capable of resolutions up to 720 x 576 for either MPEG-1 or MPEG-2. ♦...

  • Page 23: Mpeg Macroblock Structure

    For a given macroblock, the encoder must choose a coding mode. The coding mode depends on the picture type, the effectiveness of motion L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 24 Zigzag ordering concentrates the highest spatial frequencies at the end Introduction Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 25: Bitstream Syntax

    L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 26: Typical Sequence Of Frames In Display Order

    A slice provides some immunity to data errors. Should the bitstream become unreadable within a picture, the decoder should be able to Introduction Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 27: Video Decoding

    (each of the picture types I, P, and B have their own macroblock types) present in the bitstream, are used to construct a prediction of the L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 28: Audio Compression And Decompression Concepts

    The MPEG algo- rithm uses the two following processes for removing redundant audio information: ♦ Coding and quantization ♦ Psychoacoustic modelling Introduction Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 29: Audio Encoding Process (Simplified)

    , a sequence of packets , and ends with an ISO 11172 end code. The pack layer header contains a pack start code used for synchroniza- L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 30: Mpeg Audio Encoding

    1.2.1.2 Audio Frame An Audio Frame contains a slice of the audio data stream together with some supplementary data. Audio frames have the following elements: 1-10 Introduction Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 31: Audio Decoding

    ♦ Audio Data The L64005 uses the audio data to reconstruct the sampled audio data. Its format is beyond the scope of this document. The data structures for Layer I dual channel/stereo, intensity stereo, and for the more complex Layer II audio data fields are described in Sections...

  • Page 32: Mpeg-1

    fits the scale of economy for these applications that require many decoders to a few encoders. The L64005 is fully complaint with the MPEG-2 standard main profile, main level. As such it can also decode an MPEG-1 video sequence.
  • Page 33 CMYK. Cyan, Magenta, Yellow, Black. These colors are used in the print- ing industry. Chrominance. The color information portion of a signal (UV portion of YUV). See YUV. L64005 MPEG-2 Audio/Video Decoder Technical Manual 1-13 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 34 Huffman coding is a type of entropy coding that uses predeter- mined variable-length codewords. IDCT. Inverse DCT. An IDCT converts data from the frequency domain into the time (spatial) domain. IEC. International Electrotechnical Commission. 1-14 Introduction Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 35 Motion Compensation. Image compression that takes into consider- ation partial image shifts that are due to motion. L64005 MPEG-2 Audio/Video Decoder Technical Manual 1-15 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 36 SMPTE Time Code. Standard (hr:min:sec:frame) method to record and identify video frames. T-1 Channel. A T-1 channel transmits and receives digital data at 1.44 Mbits per second. 1-16 Introduction Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 37: Video Decoding

    Figure 1.7 shows how an audio/video decoding system uses the L64005. 1.5.1 The L64005 operates optimally at image sizes up to 720 x 480 pixels, Video Decoding with a frame rate of 30 fps (720 x 576 @ 25 fps for PAL). This is some- times referred to as “main level, main profile”...

  • Page 38: Post Processing

    DRAM found in non-integrated audio solutions. 1.5.3 The L64005 uses on-chip interpolation filters to interpolate images with Post Processing resolutions below 720 x 480 to full size. This allows programming pro- duced at different resolutions to be decoded and displayed on televisions with standard NTSC or PAL timing.

  • Page 39: Pes Decoding

    A user port allows you to program system options and monitor the oper- User Interface ation of the device. Errors flagged by the L64005 and user data present in this channel may be read through this port. However, the device will not maintain unread user data indefinitely.
  • Page 40 The L64005 flags the errors so that they may be masked in the display or on the audio output. An external programmable microcontroller may execute mechanisms to recover from gross errors.
  • Page 41 The system layer is parsed bit serially before the data is written to the channel buffers. The L64005 parses MPEG-2 Pack Layer and video and audio PES pack- ets only. Other types of PES packets are discarded. The video and audio streams are separated into header and payload streams and written to independent buffers in the DRAM.

  • Page 42: Video Output

    1.6.3.3 Interlaced/Chroma Field Repeat or Chroma Line Repeat Video Output The L64005 can output video to an interlace-scanned video monitor or television. The video timing circuitry must output the correct pulse train for both odd and even fields, as well as the transition between fields. The number of active scan lines in a typical field is 240, though the actual...
  • Page 43 field is dis- played twice. The L64005 may be programmed to repeat a field. The full picture can be displayed during each field of an interlaced video display system. This feature is only available when not using Reduced Memory Mode, how- ever.

  • Page 44: On-Screen Display

    MPEG Layer 1 or Layer 2 only. 1.6.5.1 Input Buffering The L64005 provides for an audio channel buffer (rate buffer) as part of the attached DRAM store. This offers considerable savings over separate audio decoders which need an additional DRAM for channel buffering when operating in conjunction with a video decoder.

  • Page 45: 1.6.5.2 Audio Output

    1.6.5.3 Audio Decode Rate Control The L64005 decodes audio data at a rate proportional to the audio sam- ple frequency. The sample frequency is either derived internally from the 27-MHz SYSCLK reference, or externally from the oversampling clock reference input, ACLK.

  • Page 46: System Controller Interface

    An external system controller (microcontroller) is responsible for test, ini- System tialization, and real-time control of the L64005. The interface between the Controller system controller and the L64005 is 8 bits wide and fully asynchronous. Interface 1.6.6.1 Device Initialization The system controller defines the operational mode of the L64005 decoder.

  • Page 47: Channel Interface

    Output pins are also provided that reflects this status. These pins are used where a hardware handshake is needed. 1.6.7 Coded bitstream data is typically written serially into the L64005. On Channel each rising edge of a serial channel clock, the decoder reads a single bit Interface and an associated data-valid signal.

  • Page 48: Features

    If the coded data in the channel is changed to a new program source, the system controller must inform the bitstream parser to stop decoding and search for a new intra-frame resynchronization point. The L64005 then freezes on the last complete anchor frame until a new sequence is acquired.
  • Page 49 ♦ Provides 8-bit Y/C output data format in interlaced or progressive scanned mode. ♦ Interfaces directly to LSI Logic's L64007, L64008, and L64108 trans- port demultiplexers on the input and off-the-shelf NTSC/PAL encod- ers on the output. ♦ Provides a complete on-chip channel buffer and display buffer con- trols.
  • Page 50 Packaged in a 160-pin copper lead frame PQFP (plastic quad flat pack). ♦ Uses low power 3.3 V process. ♦ Includes TTL compatible I/O pins. 1-30 Introduction Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 51 Section 2.8, “Group 6 Secondary Control Registers” ♦ Section 2.9, “Group 7 Secondary Control Registers” The L64005 uses an address indirection scheme to access a large num- L64005 Register ber of internal state registers using a small number of external address Overview pins.

  • Page 52: L64005 Register Map

    Video Req Channel Ready Audio Req Channel Ready Audio Stream Select Enable Audio Stream ID Aux Data Layer ID Aux Data FIFO Status (Sheet 1 of 13) Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 53 Decode Error Decode Error Mask Data FIFO Ready Data FIFO Ready Mask Decode Status (Non-maskable Interrupt) Decode Start/Stop (Sheet 2 of 13) L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 54 Stream Select Reset Video System Buffer Reset Audio System Buffer Reset Aux Data FIFO Reset User Data FIFO User Data FIFO Output (Sheet 3 of 13) Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 55 VBI1 Luma Base Address (MSB) VBI1 Chroma Base Address (LSB) VBI1 Chroma Base Address (MSB) VBI2 Luma Base Address (LSB) (Sheet 4 of 13) L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 56 Reserved Pull-down Repeat (..22.. or ..33..) 3:2 Pull-down Enable 3:2 Pull-down from Bit Stream Freeze Field (Trick Mode) Freeze Frame (Trick Mode) (Sheet 5 of 13) Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 57 Video Channel Buffer End Address (LSB) Video Channel Buffer End Address (MSB) Audio Channel Buffer Start Address (LSB) Audio Channel Buffer Start Address (MSB) L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 58 Audio Original/Home Audio Copyright Audio Channel Mode Audio Sample Frequency Audio Rate ID Audio Private Data Audio Layer ID Audio Bit Rate (Sheet 7 of 13) Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 59 Audio Skip and Repeat Status Audio Skip and Repeat Mode Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (Sheet 8 of 13) L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 60 DRAM Address [15:8] Reserved (Must be set to zero on writes.) DRAM Address [17:16] DRAM Data [7:0] DRAM Data [15:8] DRAM Data [23:16] (Sheet 9 of 13) 2-10 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 61 Post-blank Lines Serration Lines Main Lines [7:3] Scan Halflines [8:1] Main Lines [8] Main Reads Per Line (Sheet 10 of 13) L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-11 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 62 Audio System Write Address (LSB) Video Channel Buffer Write Address (LSB) Audio Channel Buffer Write Address (LSB) Video Channel Buffer Read Address (LSB) (Sheet 11 of 13) 2-12 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 63 DRAM Transfer Count (7:0) DRAM Transfer Count (15:8) Reserved Flush DRAM FIFO DRAM Transfer Mode Revision ID (Sheet 12 of 13) L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-13 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 64: Writing A Single Register

    A[2:0]. Access to these groups does not auto-increment the address register. 2-14 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 65: Address Indirection Register

    Auto Increment bit is set. CI will not automatically increment if the AI bit is not set. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-15 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 66: Status 0 Register

    AREQ sig- nal handshake. Note that AR and AREQ both assert and deassert at the same time. 2-16 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 67 The following paragraphs describe the function of bits [7:0] during a write only. Channel Start/Reset 7, W Setting CS causes the L64005 to allow data into the channel buffers. Clearing CS causes the L64005 to reset the channel buffers and not allow data to enter the buff- ers.

  • Page 68: Status 1 Register

    User Data FIFO Status [1:0], R The value contained in UDFS[1:0] indicates the status of the user data FIFO as shown in the following table: 2-18 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 69: Group 3 Interrupt Register 0

    Note that once the FIFO has overrun, the status bits stay at 11 until the register is read. The L64005 will then mark the FIFO as full until a subsequent read clears the full condition or it once again becomes overrun.

  • Page 70: Group 3 Interrupt Register

    2, R/W When DER is set, it indicates that the audio or video decoder has detected a decode error. The L64005 sets DER when any one of the error status bits in Group 6, Register 1 is set. The following table lists these bits and the corresponding error conditions.

  • Page 71: Group 4 Interrupt Register

    When set, BAV indicates that the active video portion of a field is being displayed. If enabled, this interrupt occurs once per field. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-21 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 72: Group 5 Control Register

    Enable Parallel Stream 6, R/W When set, EPS selects the parallel input as the source for the MPEG stream. When clear, EPS selects the serial input. 2-22 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 73: User Data Fifo

    Set RAF to reset the Aux Data FIFO. Reset User Data FIFO 0, W Set RUF to reset the User Data FIFO. These registers access secondary control functions inside the L64005. Group 6 The register accessed within Group 6 is selected by writing its index into Secondary the Address Indirection Register (Group 0).

  • Page 74: Group 6 Error Status Register

    CRC error may persist for one or more audio frame times, this bit will only be set once per audio frame. If it is read, 2-24 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 75: Group 6 Forward Anchor Luma Base Address

    VLCE Variable Length Code or Run-Length Error 0, R When set, VLCE indicates that the L64005 has found a variable length code that is illegal in the current context, or the combined run-length in a block exceeds 64. When the audio decoder sets VLCE, it also sets the DER bit in Group 3.

  • Page 76: Group 6 Forward Anchor Chroma Base Address

    The full address value stored in Registers 6 and 7 is in Base Address 64-byte resolution. These registers are read/write. Backward Anchor Luma Base Address (LSB) Register 6 Backward Anchor Luma Base Address (MSB) Register 7 2-26 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 77: Group 6 Backward Anchor Chroma Base Address

    The full address value stored in Registers 12 and 13 is in 64-byte Chroma Base resolution. These registers are read/write. Address L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-27 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 78: Group 6 Vbi1 Luma Base Address

    Select bit in Register 22 is clear. The full address value stored in Regis- Base Address ters 16 and 17 is in 64-byte resolution. These registers are read/write. VBI1 Chroma Base Address (LSB) Register 16 2-28 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 79: Group 6 Vbi2 Luma Base Address

    64-byte resolution. These registers are read/write. VBI2 Chroma Base Address (LSB) Register 20 VBI2 Chroma Base Address (MSB) Register 21 L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-29 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 80: Group 6 Vbi Size

    OSDAM is used to control the multiplex- ing of OSD into another video source. 2-30 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 81: Group 6 Osd Field 1 Pointer

    32-byte resolution. These registers are read/write. OSD Field 1 Address (LSB) Register 24 OSD Field 1 Address (MSB) Register 25 L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-31 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 82: Group 6 Osd Field 2 Pointer

    field of the frame during which you want to begin the pulldown, and cleared while displaying the first field of the frame during which you want to end the pulldown. 2-32 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 83: Group 6 Display Mode 1

    Refer to ECN Item 5.1 Pan and Scan from Bitstream 5, R/W Setting PSB causes the L64005 to decode the pan and scan parameter from the bitstream. Clearing PSB allows the user to set the pan and scan offsets through host software control.

  • Page 84: Group 6 Raster Mapper Increment

    Increment section entitled “Setting the Filter Raster Mapper Increment” in (Horizontal Chapter 6. This register is read/write. Filter Scale) Raster Mapper Increment Register Register 30 2-34 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 85: Group 6 Display Controller Status

    3, R This bit indicates whether an odd field is coded before an even field in the MPEG video stream. The L64005 sets ODFF either when the first field of a single frame is an odd field, or when the first field of a three field pulldown sequence is an odd field.

  • Page 86: Group 6 Video Pes Buffer Start Address

    MD96.230 Bottom/Top Field Indicator 1, R The L64005 sets BTF at the first horizontal sync after a vertical sync when Bottom Field data is being displayed. The L64005 clears BTF at the first horizontal sync after a vertical sync when Top Field data is being displayed.

  • Page 87: Group 6 Video Pes Buffer End Address

    The implied lower address bits (not shown, but required to make a full 8- byte DRAM word address) are set internally to 00000 . These registers are read/write. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-37 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 88: Group 6 Audio Pes Buffer End Address

    The implied lower address bits (not shown, but required to make a full 8-byte DRAM word address) are set internally to 00000 .These registers are read/write. 2-38 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 89: Group 6 Video Channel Buffer End Address

    The implied lower address bits (not shown, but required to make a full 8-byte DRAM word address) are set internally to 00000 These registers are read/write. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-39 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 90: Group 6 Audio Channel Buffer End Address

    Group 6 audio decoder. This register is read/write. Audio Mode Control LRP PCM[1:0] I2S MUTE EXCLK Register 48 Reserved 7, R/W This bit is reserved. 2-40 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 91: Group 6 Audio Oscillator Frequency Control

    EXCLK External Audio Clock Select 0, R/W Setting EXCLK causes the L64005 to use an externally supplied audio clock (ACLK) for the derivation of the audio sample rate. Clearing EXCLK causes the L64005 to use SYSCLK (normally 27 MHz).

  • Page 92: Group 6 Audio Parameter 0

    The Audio Parameter 0 Register returns values found in the audio stream Group 6 that describe the format and mode of the audio data. This register is read Audio only. Parameter 0 2-42 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 93 AE[1:0] OH CF ACMODE[1:0] ASF[1:0] Register 52 AE[1:0] Audio Emphasis [7:6], R AE[1:0] indicates the type of emphasis that the L64005 uses. AE[1:0] Type of Emphasis No Emphasis 50/15 Microsecond Emphasis Reserved CCITT J.17 Audio Original/Home 5, R When set, this bit indicates that the bitstream contains original data.

  • Page 94: Group 6 Audio Parameter 1

    [5:4], R LID[1:0] is parsed from the frame header. LID[1:0] indi- cates the MPEG coding layer. LID[1:0] Layer Layer 1 Layer 2 Layer 3 Reserved 2-44 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 95: Group 6 Audio Trick Modes

    1100 1101 1110 1111 Reserved Reserved 1. The L64005 does not support Free Format. The L64005 will not decode Free Format input. 2.8.33 Register 54 controls and reports the status of audio trick modes. These Group 6 registers are read/write.
  • Page 96 The ADMC[1:0] bits select from which channel, left or right, the dual mono data is output from the audio decoder. Note that this is only used when the L64005 receives dual mono audio bitstreams. The default at reset is 00 or stereo mode.

  • Page 97: Group 6 Reserved Registers

    2.8.34 Registers 55 through 63 are reserved for LSI Logic use and should not Group 6 be read or written. Reserved...

  • Page 98: Vld Parameters

    Picture Coding Type (one byte) 3 uimsbf VBV Delay (two bytes) 16 uimsbf Quant Matrix Extension Identifier (one byte) 4 uimsbf Extension (Sheet 1 of 3) 2-48 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 99 20 uimsbf Copy Number 2 (three bytes) 22 uimsbf Copy Number 3 (three bytes) 22 uimsbf (Sheet 2 of 3) L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-49 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 100 first two bytes, concatenate this value with the specified number of bits from the last byte, and treat the final 16-bits as a “simsbf”. 2-50 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 101: Group 7 Dram Control

    DRAM, the host should poll WR until it is set in order to determine that the previous write has fin- ished. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-51 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 102: Group 7 Dram Address

    NOTE: The reserved bits in Register 4 must be set to zeroes when the register is written to. DRAM Address[7:0] Register 2 DRAM Address [15:8] Register 3 Reserved DRAM Address[17:16] Register 4 2-52 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 103: Group 7 Dram Data

    DRAM Data [23:16] Register 7 DRAM Data [31:24] Register 8 DRAM Data [39:32] Register 9 DRAM Data [47:40] Register 10 L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-53 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 104: Group 7 Horizontal Sync Width

    10 bits: the eight lower bits are located in Register 15 and the remaining Width two upper bits are located in Register 19. This register is read/write. Serration Pulse Width (LSB) Register 15 2-54 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 105: Active Image Done Register

    Group 7 pulse width, horizontal blank width, active image done, and half line time Upper Bits values. This register is read/write. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-55 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 106: Group 7 Pre-Blank/Equalization

    Post-Blank/ the active image and before vertical sync) and the number of half scan Equalization lines of post-equalization pulses. Post-Equalization Lines Post-Blank Lines Register 21 2-56 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 107: Scan Half Lines Register

    Refer Line to Figure 6.9, "Display Parameters", for more information. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-57 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 108: Group 7 Display Width

    Register 26 Reserved This bit is reserved. Line Double 6, R/W Setting this bit causes display line doubling in display modes 4, 5, and 6. 2-58 Registers Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 109: Group 7 Reduced Memory Mode Control

    PAL displays need only 40. See Section 6.3, “Reduced Memory Mode”, for more informa- tion. Reserved 1, R/W This bit is reserved. L64005 MPEG-2 Audio/Video Decoder Technical Manual 2-59 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 110: Group 7 Reserved Registers

    See Section 6.3, “Reduced Memory Mode”, for more information. 2.9.20 Registers 29 through 30 are reserved for LSI Logic and should not be Group 7 read or written. Reserved...

  • Page 111: Group 7 Channel Buffer Read Address

    Display Master Mode 1, R/W When set, DMM causes the display controller on the L64005 to drive the VS and HS pins. When DMM is clear, these pins are inputs, and the L64005 locks to an exter- nal sync source.

  • Page 112: Group 7 Picture Start Code Read Address

    Audio Start Code address in the channel because of the delay caused by the internal buffering. These registers are read only. 2.9.25 Registers 43 and 47 are reserved for LSI Logic use and should not be Group 7 read or written. Reserved...

  • Page 113: Group 7 Dram Source Address Registers

    2.9.27 Registers 51 and 52 stores the DRAM transfer word count. Each time Group 7 that a block move DRAM read and write cycle completes, the L64005 DRAM Transfer decrements the value of the DRAM transfer word count and generates Count Registers an interrupt when the count reaches zero.

  • Page 114: Group 7 Revision Id Register

    Register 54 is the Revision ID Register for revisions C and higher of the Group 7 L64005. The register was unavailable on revisions A and B. The values Revision ID read from this register will be 0x2D, 0x4D, 0x6E and 0x6D for revisions Register C, D, E and F respectively.
  • Page 115 When set, VRF commands the L64005 to repeat the next I, P, or B frame. When it completes the repeat, the L64005 clears this bit to let the user know that the repeat has been completed. In this mode, the L64005 stops decoding and displays the same frame a second time.

  • Page 116: Group 7 System Clock Reference (Scr) Value

    L64005 generates an interrupt. The SCR SCR Compare Compare Value may be used for synchronization purposes. Value 2.9.33 Registers 60 through 63 are reserved for LSI Logic use and should not Group 7 be read or written. Reserved Registers...

  • Page 117: User Interface

    ♦ Section 3.5, “Audio Interface” ♦ Section 3.6, “PLL Interface” Figure 3.1 shows the logic symbol for the L64005 and its six interfaces listed below: ♦ User Interface – the 8-bit interface used for programming the L64005 internal registers and reading status ♦...

  • Page 118: L64005 Logic Symbol

    Groups 6 and 7. The interface is also used for parallel transfers of coded MPEG data. There are two separate par- allel channels for video and audio data controlled by their respective Signals Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 119 When CS is LOW, AVALID and VVALID must be HIGH if they are used in parallel channel mode. The controller can latch the data from the L64005 with the ris- ing edge of CS. During a write cycle, CS must be asserted LOW prior to data becoming valid from the con- troller to the L64005.

  • Page 120: Channel Interface

    SCLKI if either AVALID or VVALID is also asserted HIGH. ERROR is used to signal uncorrectable errors in the channel, and is subsequently used to invoke error handling in the decoder. Signals Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 121 SCLKI may be asyn- chronous to the device clock. The value on SERI is clocked into the L64005 video channel buffer on the rising edge of SCLKI if VVALID is asserted HIGH and the device is in serial stream mode.

  • Page 122: Parallel Channel Input Timing

    3.2.1 A parallel channel write request is made when the L64005 asserts VREQ Parallel Channel LOW. The write remains pending until the rising edge of VVALID signal Writes writes the data to the chip. The L64005 deasserts VREQ HIGH in response to the falling VVALID signal, then the controller is free to assert VVALID HIGH and switch off the data bus.

  • Page 123: Memory Interface

    Similarly, the L64005 asserts AREQ signal when space is available in the audio channel buffer. AREQ is deasserted HIGH when the channel is unable to accept more data. After AREQ is deasserted, the channel can accept eight more bits after eight serial clock data transfer cycles before it stops accepting data.

  • Page 124: Synchronous Dram Signals

    Synchronous DRAM Row Address Select Output SRAS drives the RAS pin on the synchronous DRAM. Synchronous DRAM Write Enable Output SWE drives the WE pin on the synchronous DRAM. Signals Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 125: Video Interface

    TESTCLK Synchronous DRAM Test Clock Input TESTCLK is used to provide a test clock to the L64005 when its internal PLL is bypassed by tying BYPASS to a logic ‘0’. BYPASS PLL Bypass Input BYPASS, when pulled to a logic ‘0’, causes the L64005’s...

  • Page 126: Master Mode

    Master Mode BLANK CREF PD[7:0] (YCbCr) MD96.20 The audio interface signals described in this section allow the L64005 to Audio Interface interface to a variety of serial PCM digital-to-analog converters. There 3-10 Signals Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 127: Pll Interface

    SYSCLK clock reference using an internal divider. Jittering the BCLK and LRCLK signals yields, on average, an accurate audio sample rate. In slave mode, the L64005 takes the oversampling clock reference provided on the ACLK pin as an accurate external DAC clock reference.

  • Page 128: External Loop Filter

    PCB. Pin 69 Loop Filter Connection For Rev. E of the L64005 the external loop filter is not required and Pin 69 is Not Connected. However, if the board in question already has the filter described below, it may remain in place without affecting the operation of the device.

  • Page 129: Channel Data Parsers

    (in particular, increase the number of Slice Layers) to decrease the propagation of errors. The L64005 therefore takes the approach of “damage control” in response to channel errors, regardless of their source. The channel switch time can be decreased by increasing the number of sequence start codes in the stream.

  • Page 130: Summary Of The Bitstream Parsing Operations

    Buffers Post-Parser Channel Read FIFO To DCT Pipeline Bit-Parallel Post-Parser MPEG VLC User Data Auxiliary Data Table FIFO FIFO Microprocessor Bus System Controller MD96.225 Video Data Flow Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 131: Conceptual System Synchronization

    4.2.1.1 Synchronization in the System Header and Packet Layer The L64005 performs system synchronization for an MPEG-1 or MPEG- 2 system layer only. The L64005 parses these layers to separate the sys- tem header from the elementary video and audio streams. The system header data is stored in separate DRAM channel buffer(s) and can be read on demand by the external controller.

  • Page 132: Synchronization At The System Level

    Errors occurring in the packet header can cause synchronization failure. An error occurs when the packet length count does not match the actual length of the packet. When an error occurs, the L64005 can optionally clear the channel buffer to limit error propagation.
  • Page 133 MPEG syntax, not a fault in the design of the L64005. However, the L64005 can detect this condition and will try to resync to the next start code.

  • Page 134: Post-Parser Operation

    Pack, System, and Packet layers. The bitstream is assumed to be time-multiplexed and contain Audio and Video packets. In Program Stream Mode, the data is strobed into the L64005 with the AVALID sig- nal. Both the Audio and Video header information is stored in the Audio PES header buffer in DRAM.
  • Page 135 MPEG bitstream, while not compliant, do not flag errors in the L64005. Group of Pictures Layer – The L64005 enters the Group of Pictures Layer from the Video Sequence Layer only if the device is synchronized to the Video Sequence Layer and no errors have been detected.
  • Page 136 Picture Layer – The L64005 enters the Picture Layer from the Group of Pictures Layer only if no errors have been detected in the Group of Pic- tures header. Errors in the header of the Picture Layer have different propagation effects depending on the picture coding type.
  • Page 137 This may be used as an attempt to acquire initial synchronization when the PTS and the DTS are very far apart. It is L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 138: Channel Buffer Operation

    MPEG Transport Layer chip. Users should ensure that some portion of the buffer still resides on the L64005 so that the decoder does not get starved of data. The minimum buffering requirement specified by MPEG-2 “main level, main profile”...

  • Page 139: User Data Buffer

    Data in the on-chip read or write FIFOs is not considered when determining the buffer full state. If the channel buffer becomes full, the L64005 flags an error and may signal an interrupt. It also stops asserting VREQ and AREQ. Data sent to the decoder at this time will be lost, which results in decode errors and error concealment.

  • Page 140: Auxiliary Data Buffer

    When set, the Data FIFO Ready (DFR) bit in the Group 3, Interrupt Reg- ister 0 indicates there is data in the user data FIFO or the auxiliary data FIFO. 4-12 Video Data Flow Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 141: Elementary Stream Decoding

    Decoding start, it continually decodes pictures at a rate controlled by the frame rate of the display system. This rate is set either by the L64005 display con- troller registers (master mode) or by an external sync signal. Once the system controller instructs the L64005 to start decoding, it...

  • Page 142: Successful And Unsuccessful Frame Skips

    Frame Skip 1. Note that this skip is unsuccessful because it did not occur within the remainder of the frame T + 3. MD96.226 4-14 Video Data Flow Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 143: Overview

    The L64005’s built-in controllers allow frame memories to decode and Overview display an MPEG bit stream. The L64005 can access memory through a 64-bit data bus in regular DRAM mode and through a 16-bit data bus in synchronous DRAM mode.The interface is optimized to operate at res- olutions up to 720 x 576 pixels.

  • Page 144: Memory Interface

    The typical set of 4-Mbit DRAMs are 70-ns devices operating in fast page Regular DRAM mode at the nominal device clock of 27 MHz. The L64005 limits the Mode allowable page length to 512 words (4096 bytes), regardless of the mem- ory type used.

  • Page 145: Mapping Of Physical Address Bus To Ba[8:0]

    DRAM Mode accesses, from both bank 0 and bank 1. In synchronous DRAM mode, the L64005 limits the page length to 128 words (1024 bytes). The L64005 also accesses bank 0 and bank 1 evenly to minimize page breaks. The L64005 SDRAM interface provides a single 12-bit row/col- umn multiplexed address bus;...

  • Page 146: Mapping Of Physical Address Bus To Sba[11:0]

    Group 7, Register 53. Other parameters related to Modes these transfers are programmable through the Group 7 external host accessing registers 48 through 52. Refer to Section 2.9.28, “Group 7 External Memory Interface Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 147 MSB. In this mode, the host accesses DRAM directly through the registers in the L64005. The host can either write to the DRAM or read from the DRAM. Host Mode Write – There are two different ways in which the host can write to the DRAM: single word writes and multiple word writes.
  • Page 148 1 should be enabled before the write routine is executed. The write routine consists of reading the appropriate status bits and writing to the proper registers as shown in Figure 5.4. External Memory Interface Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 149 Set WR Bit Multiple DRAM Words Write Complete Note: Do not change DRAM address or DRAM modes during these multiple writes. MD96.56 L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 150: Single Word Read Routine

    Group 7, Register 1 before execut- ing the read routine. Figure 5.6 illustrates the read routine for multiple word reads External Memory Interface Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 151: Multiple Word Read Routine

    Note that during the multiple read routine, if the FIFO is empty at the start of the routine, the DRAM address is incremented by 16 as the FIFO is filled. L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 152 Registers 51 and 52) indicates the total number of words to be moved. Note that the transfer begins immediately when the corresponding DRAM transfer mode is set. The L64005 clears the DRAM ready bits while the 5-10 External Memory Interface Final Rev F Copyright ©...
  • Page 153 DRAM during this time. If the host is polling the DRAM ready bits, the L64005 generates an interrupt when the count reaches zero and then sets the DRAM ready bits to indicate that the block move is complete.

  • Page 154: 5.3.4.1 Regular Dram Interface

    Access N Access A write cycle is initiated if WE is LOW when the L64005 asserts CAS LOW. WE remains LOW throughout the entire cycle (read and write cycles are not intermixed during a burst transfer to a page). In a read cycle, the L64005 asserts OE LOW while WE is HIGH.

  • Page 155: Word Accesses Vs. 81Mhz Clock Cycles In Regular Dram Mode

    Table 5.3 Word Accesses vs. Number of Number of 81MHz Clock Accesses Cycles(81 MHz) Max Bytes Cycles in Regular DRAM Mode L64005 MPEG-2 Audio/Video Decoder Technical Manual 5-13 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 156: 5.3.4.2 Synchronous Dram Interface

    81-MHZ clock controls all interface signals. A write cycle is initiated if WE is LOW when CAS is also LOW; in a read cycle, the L64005 holds WE HIGH while CAS is LOW. Please note that read and write cycles are never intermixed during a burst transfer to a page.

  • Page 157: Synchronous Dram Read And Write Timing

    SCKE SRAS SCAS (writes) (reads) SDQM Column Column Column Column SBA[10:0] SBA[11] SBD[15:0] (writes) SBD[15:0] (reads) Access Access N Access L64005 MPEG-2 Audio/Video Decoder Technical Manual 5-15 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 158: Refresh Cycles

    DRAM interfaces. 5.3.5.1 Regular DRAM Interface In the regular DRAM interface, the L64005 asserts CAS before a RAS refresh cycle. The refresh cycle immediately follows any regular access to the DRAM, and requires eleven 81-MHz clock cycles to complete. This refresh continues even if the decoder is stopped.

  • Page 159: Synchronous Dram Refresh Timing

    Memory Map of data. To optimize the data access time and minimize storage require- ments, data is stored in frame stores. In the L64005 architecture, data must be stored in a way that increases the burst length of the access.

  • Page 160: Memory Map Of L64005

    VBI1 LUMA Starting Address DRAM Start = Memory gaps are not required. They are shown only for providing space for callouts in this diagram. MD96.227 5-18 External Memory Interface Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 161: Luma Frame Organization

    VBI data pointer in real time. Different pointers access chroma and luma data in each of the data areas. The L64005 stores data in an identical format in the anchor frame, B frame, and VBI data areas to simplify the display controller and the macroblock access logic.

  • Page 162: Channel Buffer Architecture

    256-byte address range (LSB = 00000 ). The Channel end addresses are at byte 255 of the address range (LSB = 11111 (Figure 5.12 illustrates the channel buffer organization in the L64005. 5-20 External Memory Interface Final Rev F...

  • Page 163: Channel Buffer Organization In L64005

    5.5.1 The Video PES buffer stores the PES header information that corre- Video PES sponds to Video PES packets when the L64005 is programmed to be in Buffer the MPEG-2 PES mode. This buffer stores all of the header information that corresponds to video above the sequence header in the MPEG lay- ered structure.

  • Page 164: Audio Pes Buffer

    5.5.2 The Audio PES buffer stores the PES header information that corre- Audio PES sponds to Audio PES packets when the L64005 is programmed to be in Buffer the MPEG-2 PES mode. This buffer stores all the header information that corresponds to audio that is above the sequence header in the MPEG layered structure.

  • Page 165: Video Output Features

    Section 6.9, “On-Screen Display” ♦ Section 6.10, “Interrupts from the Display Controller” The L64005 outputs video eight bits at a time at the device operating fre- Video Output quency (SYSCLK). Because data is read from the frame memories in Format bursts, internal FIFOs in the L64005 can sustain a continuous data rate during the active portion of the display.

  • Page 166: Composite Sync And Composite Blank

    MD96.21 Active HIGH signals Active LOW signals 6.1.1 The L64005 contains a 2-tap vertical filter. It can be used to interpolate Post- luma lines or reposition chroma lines. There are four display output Processing 480- modes for NTSC 480-line and PAL 576-line pictures: interlaced/chroma and 576-Line field repeat without chroma filtering, interlaced/chroma field repeat with...

  • Page 167: Post-Processing Modes

    (C3 + C5)/2 0.75 x C4 + 0.25 x C6 C239 C240 1. C n are the chroma line repeat coefficients. L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 168: Post-Processing 240- And 288-Line Images

    1. L n are the luma processing coefficients. 6.1.2.3 Progressive Line Repeat/Chroma Filter Chroma needs to be oversampled 4:1. The L64005 uses a combination of line repeat and frame repeat to oversample chroma data. As before, filtering can be applied to improve the reconstructed chroma data.

  • Page 169: Selecting The Post-Processing Mode

    The host microprocessor writes these bits depending on the Post- source image characteristics. See Section 2.8.18, “Group 6 Display Processing Mode 1,” for details. Mode L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 170: Effect Of Vertical Resolution And Blanking

    The L64005 supports resolutions up to 720 x 576 pixels at its nominal Video clock frequency of 27 MHz. In addition, the L64005 displays pictures with Resolution fewer pixels using a polyphase interpolation filter to convert the input rate to the output rate of typically 720 pixels on a line. If the vertical resolution is 240 pixels, field repeat or optional vertical filter can be used to display...

  • Page 171: Reduced Memory Mode

    L64005 requires that three frame stores are allocated Memory Mode in memory. In reduced memory mode, the L64005 requires that only 2.55 frame stores be allocated in memory. Setting the RMM bit in Group 7 Register 27 activates the reduced memory mode. See Section 2.9.19, “Group 7 Reduced Memory Mode Control”...

  • Page 172: Horizontal Post-Processing Filter

    4,976,640 9,953,280 14,929,920 3.000 Reduced with 2,764,800 9,953,280 12,718,080 2.556 chroma line repeat The L64005 integrates an output interpolation filter that can be used to Horizontal Post- interpolate pixels on a scan line so that there are up to 720 pixels output Processing for each line, regardless of the input picture resolution.

  • Page 173: Frequency And Phase Response A

    0.05 -0.05 -0.1 MD94.226 Figure 6.5 Frequency and Frequency Response Phase Response B 0.025 0.05 0.075 0.125 3.14 Phase -3.14 MD95.216 L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 174: Impulse Response B

    filter banks closest to the calcu- Increment lated location. The L64005 integrates a raster mapper that increments by n/256 each output pixel. The table shows the raster mapper increment for each of a number of popular source image resolutions.

  • Page 175: Raster Mapper Increment By Source Resolution

    filter the OSD data. The resolution of the OSD data does not affect the resolution of the video data. The timing of the raster produced by the L64005 is programmable to Display Control account for the large number of possible display resolutions, line rates, Parameters input clocks, frame rates, and scanning modes.

  • Page 176: Video Timing Chain Nomenclature

    6.5.1 The L64005 has programmable timing parameters and can generate a Video Raster sync timing train that is compatible with PAL or NTSC broadcast stan- Timing dards. The nomenclature of the video timing chain is illustrated in (Master Mode) Figure 6.7.

  • Page 177: Horizontal Sync Timing

    Horizontal timing parameters are measured in terms of the device clock, and are accurate to within one clock pulse. The user must write to the control registers over the L64005 user interface to set these parameters. If the L64005 is in Master Mode, all horizontal timing parameters—equal- ization, serration, and horizontal sync pulse—must be programmed.

  • Page 178: Display Parameters

    The value is the Active Image Width of the output video (For video with horizontal width =720 pixels, “Active Image Width” would be 720 * 2 = 1440 device clocks.) Figure 6.9 shows how the L64005 registers program the horizontal and vertical video timing. Figure 6.9...
  • Page 179 525 line systems, where T=13.5MHz clock period 2. For a digital active line of 720 pixels 3. With horizontal interpolation filter disabled L64005 MPEG-2 Audio/Video Decoder Technical Manual 6-15 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 180 625 line systems, where T=13.5MHz clock period 2. For a digital active line of 720 pixels 3. With horizontal interpolation filter disabled 6-16 Video Interface and On-Screen Display Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 181: Vertical Timing Of Common Tv Systems

    6.5.1.2 Vertical Timing Vertical timing parameters are measured in half-line or full-line times, using the half-line parameter defined in the horizontal timing. The user must write to the control registers over the L64005 user interface to set these parameters. Table 6.9...

  • Page 182: For Copy Protection

    VS signal must be received every field time Pixels output from the L64005 in slave mode are based on an internally generated reference counter with respect to the HS pulse. Users must...

  • Page 183: Display Trick Modes

    6.7.1 MPEG-2 supports a variety of trick modes that are signalled in the Sys- Trick Mode tem Layer. The L64005 implements trick modes under control of the host Decoding controller using the decode start/stop and freeze frame/field features. 6.7.1.1 Fast Forward...
  • Page 184 fields times O4/E4. Note that LSI Logic recommends stopping the decoder whenever freeze frame is issued. 6-20 Video Interface and On-Screen Display Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 185: Freeze Frame For One Frame Time

    Figure 6.11 shows an example of freezing a frame for one field time. In this example, frame B2 is displayed in field times O3/E3, and then using freeze frame, it is repeated during fields times O4/E4. Note that LSI Logic recommends stopping the decoder whenever freeze frame is issued.

  • Page 186: Freeze Frame For One Field Time

    The host controller asserts the Decode Start signal at the appropriate time for the Presen- tation Unit (PU). The L64005 waits until the next PU boundary (frame or field sync, depending on coding mode) then begins to decode the pic- ture.

  • Page 187: Pull-Down Field Order

    To save memory, the beginning of B frame reconstruction always overlaps the display of the last field of the preceding frame in the L64005. This is also true of slow motion mode. A mechanism exists inside the L64005 that prevents the last field from being overwritten before it is displayed.

  • Page 188: On-Screen Display

    Undefined The L64005 integrates a flexible on-screen display controller that allows On-Screen the overlay of text and graphics on top of the decoded video. The L64005 Display digitally mixes the overlay with the decoded video before outputting it on the video port. The L64005 always displays the overlay data at the same size regardless of the resolution or mode of the video data.

  • Page 189: Pointers To Overlay Display Lists

    6.9.1.2 4 Bit/Pixel Mode Similar to its operation in 2 bit/pixel mode, in 4 bit/pixel mode, the L64005 reads overlay data from the DRAM frame stores and displays it at a rate of one pixel every two device clocks.
  • Page 190 Group 7 DRAM Data Registers. 6-26 Video Interface and On-Screen Display Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 191: Osd File Organization

    D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 More Data The following subsections describe the OSD registers. L64005 MPEG-2 Audio/Video Decoder Technical Manual 6-27 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 192: Region Attribute Bits

    Weight is zero, the output pixel is weighted 100% recon- structed picture and 0% OSD. If Mix Weight is 15, the output is 15/16 OSD and 1/16 reconstructed picture. 6-28 Video Interface and On-Screen Display Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 193: Color Fields

    If set, the Mix Weight field applies to this color. If clear, the Mix Weight field does not apply, and the pixel output is completely OSD. L64005 MPEG-2 Audio/Video Decoder Technical Manual 6-29 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 194: Color Attribute Bits

    Color Extension Bits – These bits are present in the header only if the HIC bit is set. Figure 6.18 Color Extension Bits COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11 6-30 Video Interface and On-Screen Display Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 195 COL14 Color 14 [31:16] A YCbCr triple assigned to the color palette for color 14 in this region. L64005 MPEG-2 Audio/Video Decoder Technical Manual 6-31 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 196: Alpha Blending

    The L64005 fetches bitmap data from memory sequentially and stores it in a small FIFO. The L64005 reads data from the FIFO 2 (or 4) bits at a time and matches it up against the respective pixel from the video source before it is mixed together and displayed.

  • Page 197: Conversion From 4:4:4

    In linked-list mode, the width of an OSD region is not a multiple of 32 pixels (2-bpp mode) or 16 pixels (4-bpp mode). L64005 MPEG-2 Audio/Video Decoder Technical Manual 6-33 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 198: Osd Compatibility Mode

    OSD area.The L64005 stores the address for field 1 of the first OSD in the Group 6, Index 24 and 25, OSD Field Pointer 1 Registers, in 32-byte resolution.

  • Page 199: Accessing The Overlay Bitmaps

    6.9.12 The overlay bitmaps are stored in the DRAM memory attached to the Accessing the L64005. This memory is accessed 64 bits at time through the micropro- Overlay cessor interface on the L64005. The display lists are also accessed Bitmaps through the same port.
  • Page 200 6-36 Video Interface and On-Screen Display Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 201: Audio Decoder

    48 kHz, 44.1 kHz, 32 kHz, 24 kHz, 22.05 kHz or 16 kHz. The decoder takes data from a channel buffer, which is imple- mented in the DRAM attached to the L64005. The decoder then parses the data and decompresses it. Finally, it presents the decoded PCM audio data over a serial DAC interface.

  • Page 202: Starting, Stopping And Controlling The Rate Of The Decoder

    Decoder audio frames. The L64005 allows a section of an audio frame to be repeated, or to be skipped on demand. This slows down or speeds up the effective play rate and allows the decoder to come back into synchro- nization.

  • Page 203: Setting The Dac Interface Mode

    Group 6 Registers 52 and 53 are valid. 7.2.3 The L64005 uses a simple interface for a large number of serial PCM Setting the DAC DACs. It supports both baseband and oversampling DACs. However, with...
  • Page 204 The Table 7.1 shows typical values of n and n-m for the NCO at 27 MHz . When using ACLK as f it is necessary to calculate the values for n Audio Decoder Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 205: Typical Values For Nco At 27 Mhz Fd

    A phase con- stant BLCK is generally necessary when using an oversampling DAC. For this reason, the L64005 allows for an external DAC input clock to be supplied via the ACLK pin. This is called the ‘slave mode’. This clock is still passed through the NCO as described previously to generate BCLK, but BCLK is now phase constant.

  • Page 206: Determining The Presentation Time

    Channel Data 7.2.7 The L64005 detects certain errors in the coded MPEG data, as well as Error Detection other error conditions. Table 7.2 lists the maskable interrupts that are used to indicate errors and their location. Refer to Chapter 2 for specific interrupt descriptions.

  • Page 207: Location Of Maskable Interrupts

    Group 6, Register 1, Bit 5 Audio decoding not complete by presentation time because of either channel underflow and/or corrupted data The L64005 handles the various types of audio errors encountered dur- ing decoding as follows: ♦ SYNC ERROR – The L64005 only synchronizes to syntactically cor- rect MPEG audio data.

  • Page 208: Output Control

    Output Control present the PCM data in several different ways. In addition to stereo mode, the L64005 also supports left only and right only modes. Refer to the description of the Audio Dual/Mono Channel Select Bits (Group 6, Register 54, Bits [4:3]) on page 2-45 for specific programming informa- tion.
  • Page 209 System Stream Decoding and Synchronization Chapter 8 describes the resources that the L64005 provides for parsing an MPEG System Stream and synchronizing the audio and video decod- ers. The L64005 can parse the MPEG-1 System Layer, MPEG-2 Audio and Video PES Streams, and MPEG-2 Program Streams. While the...

  • Page 210: Parsing A Program Stream

    Program Stream only switches from one PES packet to another at packet boundaries. The L64005 parses MPEG-1 system data the same way that it parses MPEG-2 system data, using a system parser between the incoming sys- tem data and the elementary stream buffers.
  • Page 211 The decoder moves the Pack Header, Packet Headers and Sys- L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 212: Parsing A Transport Stream

    8.1.2 The L64005 accepts up to two interleaved PES streams (one video, one Parsing a audio) from a Transport Stream. The Transport Stream is different from...

  • Page 213: System Parser Control Bits

    Video System Write Address Group 7, Register 32, 38, and 39 Audio System Write Address Group 7, Register 33, 38, and 39 L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 214: Dram Map Of An Mpeg-2 Packet Header Structure In The Elementary Stream With Write Pointer

    Table 8.2 DRAM Map of an MPEG-2 Packet Header Structure in the Elementary Stream with Write Pointer Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 DRAM Stream ID Packet Length Packet Length Flags Word n (MSB)

  • Page 215: Mpeg-2 Transport Encoder

    A PTS indicates the time at which the PU that results from decod- ing the AU should be presented to the user. The L64005 samples the audio PTS and video PTS with respect to the same clock reference, the System Time Clock (STC).

  • Page 216: Audio And Video Sync Train

    Audio and Video Sync train 1/30 sec Vertical Sync Video PTS PTSn-1 PTSn Samples Audio Frame Sync Audio PTS PTSn-2 PTSn-1 PTSn PTSn+1 PTSn+2 Samples System Stream Decoding and Synchronization Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 217 1152 samples per audio frame. The initial delay in the presentation time stamps supports the Video Buffer Verifier (VBV) delay. L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 218: Audio And Video Dtss And Ptss

    L64005 external system with audio and video synchronization. Note that the Synchronization L64005 does not synchronize the audio and video by itself. It provides Resources timing and event information, as well as facilities to control the audio and video rate. The external system can read internal status registers when it receives interrupts, and may program video and audio control registers to close the control loop.

  • Page 219: L64005 Mpeg-2 Audio/Video Decoder Technical Manual

    INTn+2 Interrupt ♦ The L64005 generates an interrupt when the picture header enters the video decoder as shown in Figure 8.5. A register captures the video channel read pointer at this time. This interrupt can be used to read the channel read pointer that corresponds to the picture start code.

  • Page 220: Audio And Video Decode Interrupts

    PTS, DTS, and other informa- tion in the header with the elementary coded data. ♦ The L64005 generates an interrupt each time a PES packet start code enters the system buffer as shown in Figure 8.6. 8-12...

  • Page 221: L64005 Video Skip And Repeat Frame

    Index 55. The VSFC[1:0] bits of this register allows the external host pro- Skip and Repeat cessor to command the L64005 video decoder to skip to the next I, P, or Frame B frame. Refer to the subsection entitled “Group 7 Video Trick Modes”...

  • Page 222: Video Skip

    The VRF bit in the Video Trick Mode Register allows the external host processor to command the L64005 video decoder to repeat the next I, P, or B frame. When this bit is set, the video decoder repeats the next I, P, or B frame.

  • Page 223: Decode To Display Delay

    This will typically be the next field boundary in the middle of a frame. The L64005 video decoder will skip a frame if the frame skip bits are set when the decoder reads the picture header, or after the picture header has been read but the decoder is waiting for the next PU boundary.

  • Page 224: Audio Decoder Rate Control

    Like the video decoder, the audio decoder can be programmed to adjust Audio Decoder its output rate. The L64005 allows a section of audio frame to be Rate Control repeated or skipped on request. This slows down or speeds up the effec- tive play rate and allows the decoder to resynchronize with the video.

  • Page 225: Audio Input Clock Is 256 Fs

    NCO and increases the sampling rate. This section describes a basic audio/video synchronization algorithm. Audio/Video The algorithm uses the available set of features on the L64005 that were Synchronization described in the previous sections. Technique This algorithm is not the only one that you may choose for system imple- mentation.
  • Page 226 PCR field of the transport layer, or optionally, in the ESCR field of the PES header. Because the L64005 cannot accept transport layer packets, it cannot receive the PCR. A transport device such as LSI Logic’s L64007 Transport Demultiplexer can perform clock recovery and...

  • Page 227: Clock Recovery

    PCRs. The L64005 can perform clock recovery on the ESCR. Each step of the following algorithms is implemented as an inde- pendent subroutine called by the interrupt handler routine. 8.5.1 The clock recovery mechanism for the A/V synchronization system can...

  • Page 228: Creating Audio And Video Pts List

    SCRarr time is sampled at the arrival of the PCR from the transport device. 8.5.2 When audio and video PES packets enter the L64005, they are parsed Creating Audio and stored in the external memory buffer. This is the first step in the and Video PTS decoding process.The L64005 provides four separate regions for PES...

  • Page 229: Buffer Organization In L64005 Memory

    (depending upon the stream ID field) in the PES mode, or into the audio PES header buffer in system mode. At the end of the header, the L64005 writes the current write pointer value of either the video or the audio channel buffers.

  • Page 230: Pes Header Structure

    Header Packet Bytes to Fill 8 Byte Write Padding Buffer Field Field Data Field Seq Ctr Word Pointer Length Data MD96.251 8-22 System Stream Decoding and Synchronization Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 231: List Of Pending Pus For Video And Audio

    The picture start code interrupt indicates when a picture in the channel Picture Header buffer starts decoding. Note that the L64005 actually starts decoding the Interrupt and picture on a PU boundary, which is determined by the vertical sync inter- AUX FIFO val.

  • Page 232: Pts Association With Presentation Unit

    GOTO Picture Type Routine Once the PTS from the table has been identified and the AUX FIFO Ready Interrupt occurs, the host processor must read the L64005 Auxil- iary data FIFO to determine the type of picture that is currently in the decode process.

  • Page 233: L64005 Mpeg-2 Audio/Video Decoder Technical Manual

    Fetch Previously Stored Anchor PTS for the Synchronization Is Current PTS Available? Store Current PTS for the Future Anchor Reference Return L64005 MPEG-2 Audio/Video Decoder Technical Manual 8-25 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 234: Vertical Sync Interrupt

    PCR clock recovery or optionally can be initialized from an ESCR value from the PES packet. The SCR starts to run on the L64005 27-MHz clock that, divided internally by 300, pro- vides a 90-kHz input clock. From this point, the SCR value provides a presentation time as a reference for comparison with all subsequent PTSs obtained from the bitstream.
  • Page 235 PTSn+m Write Pointer n+m Compare Write Pointer to ReadPointer Fetch PTS from Table Decode Delay to PTS Audio Error MD95.214 L64005 MPEG-2 Audio/Video Decoder Technical Manual 8-27 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 236 Expected Audio PTS to Actual PTS Comparison Routine This section describes some practical considerations for synchronizing Real System the L64005 in a real system. Many of these considerations can be man- Considerations aged through software control. Real systems can have a large amount of jitter in the bitstream. The effects of jitter show up as clock recovery errors.
  • Page 237 flexible software for video synchro- nization. This system also requires a variable rate channel. L64005 MPEG-2 Audio/Video Decoder Technical Manual 8-29 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 238 8-30 System Stream Decoding and Synchronization Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 239 Section 9.3, “Pin Summary” ♦ Section 9.4, “Packaging” Note: All specifications are for the L64005 revisions D through F. These devices are manufactured in LSI Logic’s 3.3-V, 0.5-micron LCB500K (rev. D) and 3.3-V, 0.35-micron G10 (rev. E and F) process technologies respectively, and are subject to change.

  • Page 240: Dram Write Cycle

    This section presents AC timing information for the L64005 MPEG-2 AC Timing Audio/Video Decoder. Figures 9.3 through 9.13 depict the following tim- ing relationships: ♦ Figure 9.3, “DRAM Write Cycle” ♦ Figure 9.4, “DRAM Read Cycle” ♦ Figure 9.5, “Sync DRAM Write Cycle”...

  • Page 241: Ac Test Load And Waveform For Standard Outputs

    Waveform for 3-State Outputs Output = 2.5 V 55 pF = -20 mA 3.5 V – 1.5 V 1.5 V 1.5 V L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 242: Ac Timing Values

    SCLK edge to SCAS SCLK to SBA[11:0] SCLK to write data SBD Read SBD setup before SCLK edge Read SBD hold after SCLK edge (Sheet 1 of 3) Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 243 CS falling edge to CS falling 2Tc + 7 (Write Cycle) Data setup to WAIT rising Data 3-state from CS rising (Sheet 2 of 3) L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 244 Figure 9.13) CREF, HS, VS, OSD hold ASDATA to BCLK High BCLK High to ASDATA Change LRCLK Change to BCLK High Blank Delay (Sheet 3 of 3) Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 245 Figure 9.3 DRAM Write Cycle SYSCLK BA[8:0] Column Column Column Column BD[63:0] Valid Valid Valid Valid L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 246 Figure 9.4 DRAM Read Cycle BA[8:0] Column Column Column Column BD[63:0] Valid Valid Valid Valid Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 247 Figure 9.5 Sync DRAM Write Cycle SCLK SCKE SRAS SCAS SBA[11] SBA[10:0] Column Column SBD[15:0] SDQM L64005 MPEG-2 Audio/Video Decoder Technical Manual Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 248 Figure 9.6 Sync DRAM Read Cycle SCLK SCKE SRAS SCAS SBA[11] SBA[10:0] Column Column SBD[15:0] SDQM 9-10 Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 249 Parallel Channel Write Timing AREQ, VREQ AVALID, VVALID D[7:0] (Input) MD95.202 Figure 9.8 Host Write Timing D[7:0] READ A[2:0] WAIT MD95.203 L64005 MPEG-2 Audio/Video Decoder Technical Manual 9-11 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 250 A[2:0] WAIT MD95.204 Figure 9.10 Serial Data Input SCLKI SERI AVALID VVALID 1. LSI Logic does not recommend using a gated clock on SCLKI. MD95.217 9-12 Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 251 2. In Master Mode: VSYNC & HSYNC are outputs; BLANK is output. MD95.206 Figure 9.13 Serial PCM Data BCLK Out Timing ASDATA LRCLK0 MD95.207 L64005 MPEG-2 Audio/Video Decoder Technical Manual 9-13 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 252: Absolute Maximum Ratings

    This section specifies the electrical requirements for the L64005. Four Electrical tables list electrical data in the following categories: Requirements ♦ Absolute Maximum Ratings (Table 9.3) ♦ Recommended Operating Conditions (Table 9.4) ♦ Capacitance (Table 9.5) ♦ DC Characteristics (Table 9.6) Table 9.3...

  • Page 253: Dc Characteristics

    3. Not more than one output may be shorted at a time for a maximum duration of one second. 4. These values scale proportionally for output buffers with different drive strengths. Table 9.7 summarizes the L64005 pins. The table provides the drive Pin Summary capacity of the outputs and the signal types for both output and input pins.

  • Page 254: Pin Description Summary

    TTL Output – DRAM Row Address Select TTL Output RESET Reset TTL Input – SCLKI Serial Clock In TTL Input – High (Sheet 1 of 2) 9-16 Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 255 – High Vertical Sync TTL Bidirectional High WAIT Data Wait 3-State Output DRAM Write TTL Output (Sheet 2 of 2) L64005 MPEG-2 Audio/Video Decoder Technical Manual 9-17 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 256: L64005 Ordering Information

    (Figure 9.14), and a mechanical drawing (). Table 9.8 provides ordering information for the L64005. Table 9.8 L64005 Ordering Information Order Number Device Package Type Operating Range 65042A1 L64005-F 160-pin PQFP Commercial 9-18 Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 257: Reset

    3. Pins 120 and 131 must be pulled to VDD through a resistor. A Value of 4.7K ohms is recommended. L64005 MPEG-2 Audio/Video Decoder Technical Manual 9-19 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 258 2. Reserved pins should remain unconnected unless otherwise specified (Pin 120). 3. Pin 120 must be pulled to VDD through a resistor. A value of 4.7K ohms is recommended. 9-20 Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 259: L64005 Pinout Diagram For Regular Dram 160-Pin Pqfp

    2. Reserved pins should be left unconnected unless otherwise specified.. 3. Pin 120 is reserved but should be pulled to Vdd through a 4.7K ohm resistor. L64005 MPEG-2 Audio/Video Decoder Technical Manual 9-21 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 260: L64005 Pinout Diagram For Synchronous Dram 160-Pin Pqfp

    2. R eserved pins should be left unconnected unless otherwise specified. 3. Pin 120 is reserved but should be pulled to Vdd through a 4.7K ohm resistor. 9-22 Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

  • Page 261: Mechanical Drawing

    LSI Logic marketing representative by requesting the outline drawing for package code PZ. Drawing 1 of 2 MD96.PZ L64005 MPEG-2 Audio/Video Decoder Technical Manual 9-23 Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 262 Figure 9.16 (Cont.) 160-Pin Copper Lead Frame PQFP Mechanical Drawing of 2 9-24 Specifications Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 263 ♦ Section A.4, “Engineering Practice for Mixed Voltage Systems” Special on-chip I/O buffers enable the L64005 to interface to 5-V ICs even though the on-chip power supply is only 3.3 V. This scheme meets all TTL and/or LVTTL specifications while conforming to the limits of pro- cess voltage stress .

  • Page 264: Dc Logic Levels

    ♦ an L64005 output buffer that drives a TTL input on a 5-V IC ♦ an L64005 output buffer that drives a TTL or CMOS input on a 5V IC using an open drain configuration ♦ L64005 3-state output buffer that coexists on a common bus with one or more 5-V ICs.

  • Page 265: V-Compatible Input Buffers

    Buffer For each configuration, a special purpose 5-V compatible I/O buffer is available in the technology used for L64005, which accepts signal voltage levels exceeding the 3.3-V on-chip power supply during normal system operation. 5-V compatible buffers are designed to interface to 5-V ICs without being true 5-V I/Os—they do not need a 5-V power supply on-...

  • Page 266: Ibuf (3.3V Input), Lvttl Ac Characteristics

    Propagation delay, High-to- Low 0.7 ns Nominal with F.O. = 16 of IBUFF, Transition Input Ramptime = 0.8 ns (10 - 90%) Appendix A Interfacing the L64005 to 5-V Signals Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.
  • Page 267 0.25 mA. Consider the effects of large numbers of 5-V compatible output buffers held in a static HIGH state under passive load conditions. If the L64005 holds a large number of outputs in a static HIGH state and con- sumes minimal AC power because of reduced or inhibited system clock...

  • Page 268: Dc Characteristics

    = 6 mA A.2.6.2 AC Characteristics Table A.16 shows AC characteristics for a 3-state buffer used in the L64005. All values are given for nominal process conditions (V = 3.3V, = 25 °C). External load conditions are: C = 50 pF; Input ramptime LOAD (10% to 90%) = 0.8 ns.

  • Page 269: Open Drain Outputs

    Outputs 3.3 V. If the L64005 drives signals into CMOS 5-V input buffers on the interfacing chips, these signals may require an open drain output buffer. Figure 2.3 is a block diagram of the circuitry for a 5-V compatible open drain output buffer.
  • Page 270 BVD breakdown. If you follow good engineering practices when designing your mixed voltage system, these areas of potential risk will not affect the operation or long term life of the L64005 with 5-V compat- ible I/Os from LSI Logic. Additional precautions to protect the mixed volt- age ICs are not necessary.
  • Page 271 3-state mode using a power-on- reset signal until the system logic that performs arbitration is enabled. The signals at the host interface of the L64005 are 3-stated if the CS is deasserted. The designer should take care and deassert CS during power-on procedure.
  • Page 272 A-10 Appendix A Interfacing the L64005 to 5-V Signals Final Rev F Copyright © 1996 by LSI Logic Corporation. All rights reserved.

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