DIGITAL-LOGIC MSM800SEV/SEL Technical User's Manual page 55

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The following table provides a summary of how these areas may be further divided.
Beginning Ending
00h 0Fh
10h 2Dh
2Eh 2Fh
30h 33h
34h 3Fh
40h 5Bh
5Ch 5Dh
5Eh 6Eh
6Fh 7Dh
7Eh 7Fh
CMOS Map
Location Description
00h Time of day (seconds) specified in BCD
01h Alarm (seconds) specified in BCD
02h Time of day (minutes) specified in BCD
03h Alarm (minutes) specified in BCD
04h Time of day (hours) specified in BCD
05h Alarm (hours) specified in BCD
06h Day of week specified in BCD
07h Day of month specified in BCD
08h Month specified in BCD
09h Year specified in BCD
0Ah Status Register A
Bit 7
Bits 6-4 = Time based frequency divider
Bits 3-0 = Rate selection bits that define the periodic
0Bh Status Register B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Continued...
Checksum Description
No RTC and Checksum
Yes System Configuration
No Checksum Value of 10h - 2Dh
No Standard CMOS
No Standard CMOS - SystemSoft Reserved
Yes Extended CMOS - Chipset Specific
No Checksum Value of 40h - 5Bh
No Extended CMOS - Chipset Specific
Yes Extended CMOS - Power Management
No Checksum Value of 6Fh - 7Dh
= Update in progress
interrupt rate and output frequency.
= Run/Halt
0 Run
1 Halt
= Periodic Timer
0 Disable
1 Enable
= Alarm Interrupt
0 Disable
1 Enable
= Update Ended Interrupt
0 Disable
1 Enable
= Square Wave Interrupt
0 Disable
1 Enable
= Calendar Format
0 BCD
1 Binary
= Time Format
0 12-Hour
1 24-Hour
= Daylight Savings Time
0 Disable
1 Enable
MSM800SEV/SEL/BEV/XEV/XEL Detailed Manual V1.7
55