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Ⅱ
Appendix
Circuit diagram
PW M/ M O T
PW M/ M O T
C U R /M O T
C U R /M O T
P W M /M O T
P W M /M O T
E N / M O T
E N / M O T
C U R /M O T
C U R /M O T
E N /M O T
E N /M O T
V R D -
V R D -
V R D +
V R D +
D riv e G 1
D riv e G 1
D riv e E 1
D riv e E 1
D riv e E 2
D riv e E 2
D riv e G 2
D riv e G 2
2
1
1
1
3
A
K
3
2
3
2
3
2
3
2
3
2
3
2
1
23
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