Block Diagram Of The Reference Design - Terasic TRDB-D5M Manual

Block Diagram of the Reference Design

3.7
The complete reference design is also located in the CD-ROM attached. Please
refer to the following diagram to help you in reading the code provided.
DATA
FVAL
LVAL
PCLK
CMOS
MCLK
Image
Sensor
SDAT
SCLK
Module
Figure 3.8. The block diagram of the digital camera design
The below figure for DE4 only.
DATA
FVAL
LVAL
PCLK
CMOS MCLK
Image
Sensor
SDAT
SCLK
Module
Figure 3.9. The block diagram of the digital camera design for DE4
Digital Camera Design Demonstration
Bayer Color
CMOS
Pattern Data
Sensor Data
To
Capture
30-Bit RGB
I2C Sensor Multi-Port SDRAM
Configuration
Core
Bayer Color
CMOS
Pattern Data
Sensor Data
Capture
To
30 - Bit RGB
I 2 C Sensor
Multi - Port DDR2
Configuration
Read & Write Controller
Core
21
DATA
VGA
HS
Controller
And
VS
Data Request
CLK
DATA
ADDR
Controller
CTRL
Board
DATA
DVI
HS
Controller
VS
And
Data Request
CLK
DATA
ADDR
CTRL
Board
VGA
DAC
SDRAM
DVI
TX
DDR2