Sony CFD-E90 Service Manual page 40

CFD-E90
Pin No. Pin Name
70 XT1
71 XT2
72 VDD
73
VSS
74
X1
75
X2
76 RST
77 V-CLK
78 V-DATA
79
BL-SLEEP
80
ISS1
40
I/O
I
Sub system clock input terminal (32.768 kHz)
O
Sub system clock output terminal (32.768 kHz)
— Power supply terminal (+3.3V)
— Ground terminal
I Main system clock input terminal (4.19 MHz)
O Main system clock output terminal (4.19 MHz)
System reset signal input "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
O
Serial data transfer clock signal output to the electrical volume
O
Serial data output to the electrical volume
LCD back light sleep control signal output terminal High impedance: LCD back light sleep
O
Not used
O ISS 1 on/off control signal output "H": ISS 1 on
Description