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KBR0, KBR1, KBR2
KBC0, KBC1, KBC2
to Keyboard
BKLT_EN
to Display
DP_EN_L
SIMPD0
V2
LS1_IN
LS2_IN
BATT_THERM_AD
SIM_TX
SIM_RX
U905
IrDA_EN
VIB_EN
EXT_CHG_EN
HEAD_INT_L
CLK_SELCT
TX_EN
DM_CS
TX_KEY
RX_EN
RX_ACQ
RESET
( SDTX ) BDX
( TX_CLK ) BCLKX
from / to MAGIC
BCLKR
( SDFS ) BFSR
( SDRX ) BDR
15 PIN EXT CONN.
J 600
13
DSC_EN
7
RS232_RX
6
RS232_TX
4
URXD
BATT_FDBK
from Charger
UTXD
3,8
V2
IrDA_EN
2
SW_RF
to Antenna Switch
8
EXT_CHG_EN
14
EXT_B+
EXT_B+
5
MAN_TEST_AD
1
GND
DSC_EN_AD
3
GND
DOWNLINL_AD
BATT_THERM_AD
10
GND
15
GND
9
ON / OFF
RESET
11
UPLINK
12
DOWNLINK
MIC
2
1
U902
J504
V2
HEADSET
CON.
R976
HEAD_INT_L
R977
H2, H1, H3
C14, F10, G4, H4, K5, P13
J5, J3, J2
KEYPAD
A9, A10, C5, K6, K10, M8, M11
K3
DISPLAY
WHITE_CAP
A11
INTERFACE
SPI
INTERFACE
A4
E9
SIM
E7
INTER
M
U700
F3
E
B5
FACE
M
B2
O
K1
R
C2
Y
A1
N3
A1
C1
I
C1
E2
CPU
C11
N
CTM
E2
E1
C9
T
E1
MODULE
E3
E
E10
E3
E4
R
E4
B11
P2
F
P2
A
C
D9
B6
E
B9
SERIAL
B3
INTER
DSP
B4
F1
FACE
CTM
D4
H5
A3
L1
DSC
K2
CHARGE
UART
A5
SPI
TIMER
INTERF.
INTERFACE
A6
B7
P4
H10
7
6
U500
B+
5
IRDA
F5
A7 B7
C7
D6
SPI
REAL TIME
INTERFACE
CLOCK
U900
A1
LEVEL
B2
SENSE
SHIFT
A2
G_CAP2
B3
CNTL.
ON_2
G5
C4
Logic Control
D2
C2
J2
Interface
Audio
K1
E18
Codec
VBOOST1
A5
H9
H6 H7 K9
J9
K6
E1
SR_VCC
SPKR
4
1-3
5-8
Q938
L901
ALRT
ALRT_VCC
B+
VDDS
V2
VCC_MEMIF
VDD
V3
VCCA
MAGIC SPI
ADDRESS BUS
DATA BUS
SR_VCC
A6
CE8
CE2
B2
U702
CE3
SRAM
A1
R_W
G5
BATT CON.
STBY_DL
J604
BATT_SER_DATA
4
CHRG_EN
EXT_B+
B+
Q901
1
8
BATT+
CR903
R913
EXT_B+
CR903
BATT+
3
Q900
CHRG_EN
8
4
ISENSE
D9
CHRGC
E8
CLK
F6
1
J803
RESET
SIM
J7
2
SIM_I/O
Con.
J8
6
4
3
VSIM1
K7
LS1_IN
G6
LS2_IN
K10
SIM_TX
H8
SIM_RX
C8
PWR_SW
G4
STBY_DL
G9
VREF
VREF
2.775V,for Magic
REG.
V3
B5
V3
1,8V, for WhiteCap
REG.
J5
V2
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
V2
REG.
A6
V1
5.0V, for DSC Bus, Negative Voltage Regulator
V1
REG.
C6
VSIM
VSIM1
3.0 or 5.0V, for SIM Card Circuit
REG.
C5, B6
A10, C10
REG.
B10
CR902
V_BOOST1
Internal GCap use only (VSIM1, LS_V1)
to Backlight
ALRT_VCC
V2
SR_VCC
A4, E1, F5
A6
CE8
RESET
U703
B4
U701
B5
SRAM
R_W
EPROM
G5
R_W
EEPROM
B3
CE0
D7
CE1
F8
4
1
GND
U904
1
2
3
V1
U903
2
1
BATT_SER_DATA
BATT_THERM_AD
VREF
DEEP SLEEP
STBY_DL
V1_SW
V1
V2
CIRCUIT
BATT_FDBK
to J600
( WhiteCap )
GSM SERVICE SUPPORT GROUP
LEVEL 3 AL Block Diagram
Michael Hansen, Ray Collins, Ralf Lorenzen,
to MAGIC
J902
A0
3
D0-D7
5-12
V1-V5
INT.
C702-C706
DIV.
13
V2
2
RESET
GND
14
R_W
4
DP_EN_L
15
( -10V )
1
-10V
KBR0, KBR1, KBR2
to WhiteCap
-5V
KBC0, KBC1, KBC2
KEYPAD
PWR_SW
from G CAP2
BACK
ALERT_VCC
LIGHT
from G CAP2
C
B
BKLT_EN
Q907
from WhiteCap
E
J5001 J5002
VIB_EN
1
U501
4
5
VIBRA CON.
B+
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
18.07.00
Rev. 1.0
Tri Band GPRS Leap
Page 2
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