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6-4.
SCHEMATIC DIAGRAM •
See page 25 for IC Block Diagrams.
Q Q
7
3
T
E
L
1
3
9
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and
1
/
W or less unless otherwise
4
specified.
•
: internal component.
f
• C : panel designation.
• U : B+ Line.
• H : adjustment for repair.
• AC voltage readings in the REC bias oscillator with a level
meter.
• Power voltage is dc 1.5 V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal conditions.
no mark : PB (F: FWD, R: REV)
(
) : REC (F: FWD, R: REV)
〈〈
〉〉 : DOUBLE REC
[
] : VOICE-UP PB
{
} : REC PAUSE (VOR)
∗
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 MΩ).
w w w
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
E
: PB
a
: REC
N
: MIC
– 21 –
1
5
1
6
3
4
2
2
9
6
5
1
3
x
a
o
y
.
i
– 22 –
http://www.xiaoyu163.com
5
0
Q
Q
3
7
6
3
u
1
6
3
.
http://www.xiaoyu163.com
2
4
8
9
9
1
5
1
5
0
8
9
2
m
c
o
– 23 –
TCS-100DV
• Waveforms
2
8
9
9
1 Q333 (emitter) (REC mode)
20 mV/DIV, 10 µs/DIV
41 mVp-p
17.5 µs
2 Q309 (base) (REC mode)
500 mV/DIV, 10 µs/DIV
1.3 Vp-p
17.5 µs
3 IC701 5 (XO)
2 V/DIV, 100 ns/DIV
4
9
8
2
9
9
4.3 Vp-p
250 ns
4 IC601 wl (PULSE)
200 mV/DIV, 2 ms/DIV
430 mVp-p
4.6 ms
5 IC702 4 (LX)
1 V/DIV, 2 µs/DIV
4 Vp-p
10.5 µs
– 24 –
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