Denon DN-C680 Service Manual page 17

Pin No. Symbol I/O
36 OFT I Off track signal input ("H": off track).
37 TRCRS I Track cross signal input.
38 RFDET I RF detecting signal input ("L": detect).
39 BDO I Drop out signal input ("H": drop out).
40 LDON O Laser ON signal output ("H": ON).
41 PLLF2 I/O Loop filter terminal for PLL.
42 PLAY O Play signal output ("H": play).
43 WVEL O Double speed status signal output.
44 ARF I RF signal input.
45 IREF I Reference current input terminal.
46 DRF I Bias terminal for DSL.
47 DSLF I/O Loop filter terminal for DSL.
48 PLLF I/O Loop filter terminal for PLL.
49 VCOF I/O Loop filter terminal for VCO.
50 AVDD2 Power supply for analog circuit (for DSL, PLL, DA output sections).
51 AVSS2 GND for analog circuit (for DSL, PLL, DA output sections).
52 CK384 O 384 fs clock output.
53 PCK O PLL extract clock output (fPCK=4.321MHz).
54 TOFS O Tracking offset adjust signal output.
55 SUBC O Subcode serial output data output.
56 SBCK I Clock input for subcode serial output.
57 VSS GND for osc. circuit.
58 X1 I X'tal osc. circuit input terminal. f=16.9344MHz or 33.8688MHz.
59 X2 O X'tal osc. circuit output terminal.
60 VDD Power supply for osc. circuit.
61 BYTCK O Byte clock output.
62 CLDCK O Subcode frame clock signal output (fCLDCK=7.35kHz).
63 FCLK O X'tal frame clock output (fFCLK=7.35kHz).
64 IPFLAG O Interpolation flag output ("H": interpolation).
65 FLAG O Flag output.
66 CLVS O Spindle servo phase sync state signal output ("H":CLV, "L":rough servo).
67 CRC O Subcode CRC check result output ("H":OK, "L":NG).
68 DEMPH O Deemphasis detecting signal output ("H":ON).
Flag 6 output at SSEL:"H"(RAM address reset generating signal by Jitter margin over of CLV servo.
69 RESY O "L":address reset generates). RESY output at SSBL:"L"(Re-sync signal output of frame sync. "H": sync,
"L":out sync).
70 SDAT48 O 48 fs serial data output.
71 TEST I Test terminal (normally "H").
72 AVDD1 Power supply for digital circuit.
73 LRCK48 O 48 fs L, R discrimination signal output.
74 AVSS1 GND for digital circuit.
75 BCLK48 O 48 fs bit clock output for SDAT48.
76 RSEL I RF signal polarity specify terminal (RSEL="H" at brightness level "H". RSEL="L" at brightness level "L").
77 CSEL I X'tal osc. frequency specify terminal,, X'tal osc. freq. 33.8688MHz:CSEL"H", 16.9344MHz:CSEL"L".
78 PSEL I Test terminal (normally "L").
79 MSEL I SMCK terminal. Output frequency shifting terminal ("H":SMCK=8.4672MHz,"L":SMCK=4.2336MHz).
80 SSEL I Sub Q teminal. Output mode shifting terminal ("H":Q code buffer using mode).
Function
17
DN-C680 17