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Digital Equipment 21143 Reference Manual

Pci/cardbus 10/100-mb/s ethernet lan controller
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Digital Semiconductor 21143
PCI/CardBus 10/100-Mb/s Ethernet
LAN Controller
Hardware Reference Manual
Order Number: EC–QWC4D–TE
Revision/Update Information: This manual supersedes the Digital Semiconductor
Digital Equipment Corporation
Maynard, Massachusetts
http://www.digital.com/semiconductor
21143 PCI/CardBus 10/100-Mb/s Ethernet LAN
Controller Hardware Reference Manual
(EC–QWC4C–TE).

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Summary of Contents for Digital Equipment 21143

  • Page 1 Digital Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet LAN Controller Hardware Reference Manual Order Number: EC–QWC4D–TE Revision/Update Information: This manual supersedes the Digital Semiconductor 21143 PCI/CardBus 10/100-Mb/s Ethernet LAN Controller Hardware Reference Manual (EC–QWC4C–TE). Digital Equipment Corporation Maynard, Massachusetts http://www.digital.com/semiconductor...
  • Page 2 Digital Equipment Corporation makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent rights, nor do the descriptions contained in this publication imply the granting of licenses to make, use, or sell equipment or software in accordance with the description.

  • Page 3: Table Of Contents

    21143 Pinout........
  • Page 4 3.2.2 Host CSRs ........... 3–18 3.2.2.1 Bus Mode Register (CSR0–Offset 00H).
  • Page 5 5–13 5.5.2.1 21143-Initiated Termination ........5–13 5.5.2.2 Memory-Controller-Initiated Termination .
  • Page 6 6.2.1 Receivers and Drivers ......... . 6–6 6.2.2 Manchester Decoder .
  • Page 7 21143 Magic Packet Format ........
  • Page 8 DNA CSMA/CD Counters and Events Support CSMA/CD Counters ..........B–1 Hash C Routine Little Endian Architecture Hash C Routine .
  • Page 9 Examples 4–1 Perfect Filtering Buffer................... 4–21 4–2 Imperfect Filtering Buffer ..................4–24 8–1 21143 Magic Packet Fields ................... 8–25...
  • Page 10 21143 Pinout Diagram (Top View) ........
  • Page 11 21143-Initiated Disconnect Cycle ........
  • Page 12 Tables 2–1 Functional Description of 21143 Signals ....... 2–4 3–1 Configuration Registers Mapping .
  • Page 13 3–44 Port and Data Rate Selection ........3–38 3–45 Loopback Operation Mode .
  • Page 14 Magic Packet Format for the 21143 ........
  • Page 15 Controller Hardware Reference Manual describes the operation of the Digital Semiconductor 21143 10/100-Mb/s Ethernet LAN Controller (also referred to as the 21143). This manual is for designers who use the 21143. Manual Organization This manual contains eight chapters, six appendixes, and an index.
  • Page 16 In Chapters 3, 4, and 8, all shaded bits in the figures are reserved and should be written by the driver as 0. This feature is not supported on the 21143–PA and the 21143–TA.

  • Page 17: Introduction

    (PCI) local bus or the CardBus. The 21143 interfaces to the host processor by using onchip command and status registers (CSRs) and a shared host memory area, set up mainly during initialization.

  • Page 18: Features

    Features 1.2 Features The 21143 has the following features: • Contains onchip PCS and scrambler/descrambler for 100BASE-TX • Contains onchip integrated AUI port and a 10BASE-T transceiver • Supports autodetection between 10BASE-T, AUI, and MII/SYM ports • Supports IEEE 802.3 autonegotiation algorithm of full-duplex and half-duplex operation for 10 Mb/s and 100 Mb/s (NWAY) •...

  • Page 19: Microarchitecture

    Supports SecureON,™ which is a security feature that can be added to the Advanced Micro Device’s Magic Packet technology. 1.3 Microarchitecture The following list describes the 21143 hardware components, and Figure 1–1 shows a block diagram of the 21143: •...
  • Page 20 Microarchitecture • Serial ROM port—Provides a direct interface to a MicroWire ROM for storage of the Ethernet address and system parameters • General-purpose register—Enables software use for input or output functions and LEDs • DMA—Contains independent receive and transmit controller and handles data transfers between CPU memory and onchip memory •...

  • Page 21: Block Diagram

    Microarchitecture Figure 1–1 21143 Block Diagram Boot ROM/ Board External Serial Control PCI/CardBus Register and LEDs General- Boot Serial PCI/CardBus Purpose Interface Register Port Port FIFO FIFO Physical Coding Sublayer (PCS) SIA Interface NWAY Scrambler/ Descrambler 10BASE-T MII/SYM Interface Interface...

  • Page 23: Signal Descriptions

    Signal Descriptions This chapter describes the 21143 signals. 2.1 21143 Pinout The 21143 is offered in two package styles: a 144-pin PQFP and a 144-pin TQFP. Figure 2–1 shows the 21143 pinout used by both package types. Signal Descriptions 2–1...

  • Page 24: Pinout Diagram (Top View)

    21143 Pinout Figure 2–1 21143 Pinout Diagram (Top View) LJ-04940.WMF 2–2 Signal Descriptions...
  • Page 25 Signal Descriptions 2.2 Signal Descriptions The following terms describe the 21143 pinout used in Table 2–1: • Address phase Address and appropriate bus commands are driven during this cycle. • Data phase Data and the appropriate byte enable codes are driven during this cycle.

  • Page 26: Functional Description Of 21143 Signals

    Signal Descriptions Table 2–1 provides a functional description of each of the 21143 signals. These signals are listed alphabetically. Table 2–1 Functional Description of 21143 Signals (Sheet 1 of 8) Signal Type Number Description ad<31:0> 32-bit PCI address and data lines. Address and data bits are Figure 2–1.
  • Page 27 Device select is asserted by the target of the current bus access. When the 21143 is the initiator of the current bus access, it expects the target to assert devsel_l within 5 bus cycles, confirming the access. If the target does not assert devsel_l within the required bus cycles, the 21143 aborts the cycle.
  • Page 28 • A status pin that provides an LED that indicates that the 10BASE-T link integrity test has completed successfully after the link was down. gnt_l Bus grant asserts to indicate to the 21143 that access to the bus is granted. idsel Initialization device select asserts to indicate that the host is issuing a configuration cycle to the 21143.
  • Page 29 When the 21143 is the bus master, irdy_l is asserted during write operations to indicate that valid data is present on the 32-bit ad lines. During read operations, the 21143 asserts irdy_l to indicate that it is ready to accept data.
  • Page 30 The data is synchronized to the rising edge of the sym_tclk signal. Parity is calculated by the 21143 as an even parity bit for the 32-bit ad and 4-bit c_be_l lines. During address and data phases, parity is calculated on all the ad and c_be_l lines whether or not any of these lines carry meaningful information.
  • Page 31 Parity error asserts when a data parity error is detected. When the 21143 is the bus master and a parity error is detected, the 21143 asserts both CSR5 bit 13 (fatal bus error) and CFCS bit 24 (data parity report). Next, it completes the current data burst transaction, then stops operation.
  • Page 32 JTAG data out is used to serially shift test data and instructions out of the 21143 during JTAG test operations. JTAG test mode select controls the state operation of JTAG testing in the 21143. If the JTAG port is unused this pin may be left unconnected. tp_rd–...
  • Page 33 Signal Descriptions Table 2–1 Functional Description of 21143 Signals (Sheet 8 of 8) Signal Type Number Description Ground pins. Figure 2–1. xtal1 20-MHz crystal input or crystal oscillator input. xtal2 Crystal feedback output pin used for crystal connections only. If this pin is unused, then it should be unconnected Signal Descriptions 2–11...

  • Page 35: Registers

    The 21143 enables a full software-driven initialization and configuration. This permits the software to identify and query the 21143. The 21143 treats configuration space write operations to registers that are reserved as no-ops. That is, the access completes normally on the bus and the data is discarded.

  • Page 36: Configuration Register Mapping

    Configuration Operation 3.1.1 Configuration Register Mapping Table 3–1 lists the definitions and addresses for the configuration registers. Table 3–1 Configuration Registers Mapping Configuration Register Identifier I/O Address Offset Identification CFID Command and status CFCS Revision CFRV Latency timer CFLT Base I/O address CBIO Base memory address CBMA...

  • Page 37: Configuration Registers

    The 21143 implements 11 configuration registers. These registers are described in the following subsections. 3.1.2.1 Configuration ID Register (CFID–Offset 00H) The CFID register identifies the 21143. Figure 3–1 shows the CFID register bit fields and Table 3–2 describes the bit fields. Figure 3–1 CFID Register Bit Fields...

  • Page 38: Command And Status Configuration Register (Cfcs-Offset 04H)

    (CFCS<31:16>). The command register provides control of the 21143’s ability to generate and respond to PCI cycles. When 0 is written to this register, the 21143 logically disconnects from the PCI bus for all accesses except configuration accesses.

  • Page 39: Cfcs Register Bit Fields Description

    Data Parity Report This bit sets when the following conditions are met: • The 21143 asserts parity error perr_l or it senses the assertion of perr_l by another device. • The 21143 operates as a bus master for the operation that caused the error.

  • Page 40: Cfcs Register Access Rules

    Bit Type Description Command Parity Error Response When set, the 21143 asserts fatal bus error (CSR5<13>) after it detects a parity error. When reset, any detected parity error is ignored and the 21143 continues normal operation. Parity checking is disabled after a hardware reset.

  • Page 41: Configuration Revision Register (Cfrv-Offset 08H)

    21143 revisions. Step Number Indicates the 21143 step number and is equal to 1H (chip revision B). This number is incremented for subsequent 21143 steps within the current revision. Table 3–7 lists the access rules for the CFRV register.

  • Page 42: Configuration Latency Timer Register (Cflt-Offset 0Ch)

    15:8 Configuration Latency Timer Specifies, in units of PCI bus clocks, the value of the latency timer of the 21143. When the 21143 asserts frame_l, it enables its latency timer to count. If the 21143 deasserts frame_l prior to count expiration, the content of the latency timer is ignored.

  • Page 43: Configuration Base I/O Address Register (Cbio-Offset 10H)

    Configuration Operation 3.1.2.5 Configuration Base I/O Address Register (CBIO–Offset 10H) The CBIO register specifies the base I/O address for accessing the 21143 CSRs (CSR0–15). For example, if the CBIO register is programmed to 1000H, the I/O address of CSR15 is equal to CBIO + CSR15-offset for a value of 1078H (Table 3–24).

  • Page 44: Configuration Base Memory Address Register (Cbma-Offset 14H)

    Description 31:7 Configuration Base Memory Address Defines the base address assigned for mapping the 21143 CSRs. This field value is 0 when read. Memory Space Indicator Determines that the register maps into the memory space. The value in this field is 0.

  • Page 45: Configuration Card Information Structure Register (Ccis-Offset 28H)

    PCI cycles and starts 50 cycles after hardware reset deassertion. If the CCIS is accessed by the host before its content is loaded from the serial ROM, the 21143 responds with retry termination on the PCI bus. The value is 0 if the serial ROM data integrity check fails.

  • Page 46: Subsystem Id Register (Csid-Offset 2Ch)

    50 cycles after hardware reset deassertion. If the CSID is accessed by the host before its content is loaded from the serial ROM, the 21143 responds with retry termination on the PCI bus. The value is 0 if the serial ROM data integrity check fails.

  • Page 47: Expansion Rom Base Address Register (Cber-Offset 30H)

    0, indicating that the expansion ROM size is up to 256KB. This field value is 0 when read Expansion ROM Enable Bit The 21143 responds to its expansion ROM accesses only if the memory space access bit (CFCS<1>) and the expansion ROM enable bit are both set to 1. Registers...

  • Page 48: Configuration Interrupt Register (Cfit-Offset 3Ch)

    3.1.2.10 Configuration Interrupt Register (CFIT–Offset 3CH) The CFIT register is divided into two sections: the interrupt line and the interrupt pin. CFIT configures both the system’s interrupt line and the 21143 interrupt pin connection. Figure 3–10 shows the CFIT register bit fields.

  • Page 49: Configuration Device And Driver Area Register (Cfdd-Offset 40H)

    Field Description 15:8 Interrupt Pin Indicates which interrupt pin the 21143 uses. The 21143 uses INTA# and the read value is 01H. Interrupt Line Provides interrupt line routing information. The basic input/output system (BIOS) writes the routing information into this field when it initializes and configures the system.

  • Page 50: Cfdd Register Bit Fields Description

    When the activity is completed, the 21143 reenters snooze mode. When this bit is reset, the 21143 exits snooze mode. Note that this bit should not be asserted together with bit 31 (sleep mode) in this register.

  • Page 51: Csr Operation

    CSR Operation 3.2 CSR Operation The 21143 CSRs are located in the host I/O or memory address space. The CSRs are quadword aligned, 32 bits long, and must be accessed using longword instructions with quadword-aligned addresses only. Reserved bits should be written with 0. Failing to do this could cause Note: incompatibility problems with a future version of the 21143.

  • Page 52: Host Csrs

    CSR Operation 3.2.2 Host CSRs The 21143 implements 16 CSRs (CSR0 through CSR15), which can be accessed by the host. 3.2.2.1 Bus Mode Register (CSR0–Offset 00H) CSR0 establishes the bus operating modes. Figure 3–12 shows the CSR0 bit fields. Figure 3–12 CSR0 Bus Mode Register...
  • Page 53 When reset, the 21143 operates in little endian mode. 19:17 TAP—Transmit Automatic Polling When set and the 21143 is in a suspended state because a transmit buffer is unavailable, the 21143 performs a transmit automatic poll demand (Table 3–26). This feature is not active in snooze mode.
  • Page 54 Indicates the maximum number of longwords to be transferred in one DMA transaction. If reset, the 21143 burst is limited only by the amount of data stored in the receive FIFO (at least 16 longwords), or by the amount of free space in the transmit FIFO (at least 16 longwords) before issuing a bus request.

  • Page 55: Transmit Automatic Polling Intervals

    CSR Operation Table 3–26 Transmit Automatic Polling Intervals Polling Interval CSR0<19:17> 10BASE-T/AUI 10-Mb/s MII/SYM 100-Mb/s MII/SYM TAP Disabled TAP Disabled TAP Disabled 200 µs 800 µs 80 µs 800 µs 320 µs 3.2 ms 640 µs 1.6 ms 6.4 ms 12.8 µs 51.2 µs 5.12 µs...

  • Page 56: Transmit Poll Demand Register (Csr1-Offset 08H)

    31:0 TPD–Transmit Poll Demand (Write Only) When written with any value, the 21143 checks for frames to be transmitted. If no descriptor is available, the transmit process returns to the suspended state and CSR5<2> is not asserted. If the descriptor is available, the transmit process resumes.

  • Page 57: Receive Poll Demand Register (Csr2-Offset 10H)

    The CSR3 descriptor list base address register is used for receive buffer descriptors, and the CSR4 descriptor list base address register is used for transmit buffer descriptors. In both cases, the registers are used to point the 21143 to the start of the appropriate descriptor list.

  • Page 58: Csr3 Register Bit Field

    Note: The descriptor lists reside in physical memory space and must be long- word aligned. The 21143 behavior is UNPREDICTABLE when the lists are not longword aligned. Writing to either CSR3 or CSR4 is permitted only when its respective process is in the stopped state.

  • Page 59: Status Register (Csr5-Offset 28H)

    Transmit process stopped 3.2.2.5 Status Register (CSR5–Offset 28H) The status register (CSR5) contains all the status bits that the 21143 reports to the host. CSR5 is usually read by the driver during interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. CSR5 bits are not cleared when read.

  • Page 60: Csr5 Register Bit Fields

    CSR Operation Figure 3–17 shows the CSR5 register bit fields. Figure 3–17 CSR5 Register Bit Fields 25 24 23 22 21 20 19 18 17 16 15 10 9 8 7 6 5 2 1 0 LC - Link Changed GPI - General-Purpose Port Interrupt EB - Error Bits TS - Transmission Process State...

  • Page 61: Csr5 Register Bit Fields Description

    CSR Operation Table 3–37 describes the CSR5 register bit fields. Table 3–37 CSR5 Register Bit Fields Description (Sheet 1 of 4) Field Description LC—Link Changed Indicates that the 100BASE-T link status has changed from link pass to link fail or from link fail to link pass.
  • Page 62 Indicates that the 21143 has filled the first data buffer of the packet. Receive interrupt (CSR5<6>) automatically clears this bit. FBE—Fatal Bus Error Indicates that a bus error occurred (Table 3–38). When this bit is set, the 21143 disables all of its bus access operations. LNF—Link Fail Indicates a transition to the link fail state in the twisted-pair port.
  • Page 63 Link fail interrupt (CSR5<12>) automatically clears this bit. TJT—Transmit Jabber Timeout Indicates that the transmit jabber timer expired, meaning that the 21143 transmitter had been excessively active. The transmission process is aborted and placed in the stopped state. This event causes the transmit jabber timeout TDES0<14> flag to assert.

  • Page 64: Transmit Process State Transitions

    Indicates that the next descriptor on the transmit list is owned by the host and cannot be acquired by the 21143. The transmission process is suspended. Table 4–14 explains the transmit process state transitions. To resume processing transmit descriptors, the host should change the ownership bit of the descriptor and then issue a transmit poll demand command, unless transmit automatic polling (Table 3–26) is enabled.

  • Page 65: Fatal Bus Error Bits

    CSR Operation Table 3–38 lists the bit codes for the fatal bus error bits. Table 3–38 Fatal Bus Error Bits CSR5<25:23> Error Type Parity error Master abort Target abort Reserved Reserved The only way to recover from a parity error is by setting software reset (CSR0<0>=1). Table 3–39 lists the bit codes for the transmit process state.

  • Page 66: Receive Process State

    CSR Operation Table 3–40 lists the bit codes for the receive process state. Table 3–40 Receive Process State CSR5<19:17> Process State Stopped—RESET or STOP RECEIVE command Running—Fetching receive descriptor Running—Checking for end of receive packet before prefetch of next descriptor Running—Waiting for receive packet Suspended—Unavailable receive buffer Running—Closing receive descriptor...

  • Page 67: Operation Mode Register (Csr6-Offset 30H)

    CSR Operation 3.2.2.6 Operation Mode Register (CSR6–Offset 30H) The operation mode register (CSR6) establishes the receive and transmit operating modes and commands. CSR6 should be the last CSR to be written as part of initialization. Figure 3–18 shows the CSR6 register bit fields. Figure 3–18 CSR6 Register Bit Fields 31 30 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

  • Page 68: Csr6 Register Bit Fields Description

    When set, enables the enhanced resolution of capture effect on the network (Table 6–7). Digital recommends that this bit be set together with CSR6<17>. When clear, the 21143 disables the enhanced resolution of capture effect on the network. RA—Receive All When set, all incoming packets will be received, regardless of the destination address.
  • Page 69 The transmit process must be in the stopped state to change these bits (CSR6<15:14). ST—Start/Stop Transmission Command When set, the transmission process is placed in the running state, and the 21143 checks the transmit list at the current position for a frame to be transmitted.
  • Page 70 When reset, the internal backoff counter is not affected by the carrier activity. IF—Inverse Filtering (Read Only) When set, the 21143 operates in an inverse filtering mode. This is valid only during perfect filtering mode (Table 3–46 and Table 4–8).
  • Page 71 (Table 4–8). SR—Start/Stop Receive When set, the receive process is placed in the running state. The 21143 attempts to acquire a descriptor from the receive list and processes incoming frames. Descriptor acquisition is attempted from the current position in the list, which is the address set by CSR3 or the position retained when the receive process was previously stopped.

  • Page 72: Transmit Threshold

    CSR Operation Table 3–43 lists the threshold values in bytes. Table 3–43 Transmit Threshold CSR6<18> = 0 CSR6<18> = 1 CSR6<18> = 1 CSR6<21> CSR6<15:14> CSR6<22> = X CSR6<22> = 1 CSR6<22> = 0 1024 Store and Store and Store and forward forward forward...

  • Page 73: Loopback Operation Mode

    CSR Operation Table 3–45 selects the 21143 loopback operation modes. Table 3–45 Loopback Operation Mode CSR6<11:10> Operation Mode Normal Internal loopback External loopback The selected port is placed in the internal loopback mode of operation. The PCS functions (CSR6<23>) and the scrambler function (CSR6<24>) are also tested.

  • Page 74: Csr6 Register Access Rules

    CSR Operation Table 3–47 describes the only conditions that permit change to a field when modifying values to the CSR6 register. Table 3–47 CSR6 Register Access Rules Category Description Value after reset 32000040H Read access rules — Write access rules * CSR6<22>...

  • Page 75: Interrupt Enable Register (Csr7-Offset 38H)

    CSR Operation 3.2.2.7 Interrupt Enable Register (CSR7–Offset 38H) The interrupt enable register (CSR7) enables the interrupts reported by CSR5 (Section 3.2.2.5). Setting a bit to 1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled. Figure 3–19 shows the CSR7 register bit fields.

  • Page 76: Csr7 Register Bit Fields Description

    CSR Operation Table 3–48 describes the CSR7 register bit fields. Table 3–48 CSR7 Register Bit Fields Description (Sheet 1 of 4) Field Description LCE—Link Changed Enable When this bit and the abnormal interrupt summary enable bit (CSR7<15>) are set, the link changed interrupt (CSR5<27>) is enabled.
  • Page 77 CSR Operation Table 3–48 CSR7 Register Bit Fields Description (Sheet 2 of 4) Field Description ERE—Early Receive Interrupt Enable When this bit and the normal interrupt summary enable bit (CSR7<16>) are set, the early receive interrupt (CSR5<14>) is enabled. When this bit is reset, the early receive interrupt (CSR5<14>) is disabled. FBE—Fatal Bus Error Enable When this bit and the abnormal interrupt summary enable bit (CSR7<15>) are set, the fatal bus error interrupt (CSR5<13>) is enabled.
  • Page 78 CSR Operation Table 3–48 CSR7 Register Bit Fields Description (Sheet 3 of 4) Field Description RUE—Receive Buffer Unavailable Enable When this bit and the abnormal interrupt summary enable bit (CSR7<15>) are set, the receive buffer unavailable interrupt (CSR5<7>) is enabled. When this bit is reset, the receive buffer unavailable interrupt (CSR5<7>) is disabled.

  • Page 79: Missed Frames And Overflow Counter Register (Csr8-Offset 40H)

    CSR Operation Table 3–48 CSR7 Register Bit Fields Description (Sheet 4 of 4) Field Description TSE—Transmit Stopped Enable When this bit and the abnormal interrupt summary enable bit (CSR7<15>) are set, the transmit process stopped interrupt (CSR5<1>) is enabled. When this bit is reset, the transmit process stopped interrupt (CSR5<1>) is disabled. TIE—Transmit Interrupt Enable When this bit and the normal interrupt summary enable bit (CSR7<16>) are set, the transmit interrupt (CSR5<0>) is enabled.

  • Page 80: Boot Rom, Serial Rom, And Mii Management Register (Csr9-Offset 48H)

    CSR Operation Table 3–50 CSR8 Register Bit Fields Description Field Description OCO—Overflow Counter Overflow (Read Only) Sets when the FIFO overflow counter overflows; resets when CSR8 is read. 27:17 FOC—FIFO Overflow Counter (Read Only) Indicates the number of received frames discarded because of receive FIFO overflow.

  • Page 81: Csr9 Register Bit Fields

    When clear the PHY is in write operation mode. MDO—MII Management Write Data Specifies the value of the data that the 21143 writes to the PHY by way of pin mii_mdio. MDC—MII Management Clock MII management data clock (mii_mdc) is an output signal to the PHY. It is used as a timing reference.
  • Page 82 Bit 3, Data Out—This pin serially shifts the read data from the serial ROM device to the 21143. Bit 2, Data In—This pin serially shifts the write data from the 21143 to the serial ROM device. Bit 1, Serial ROM Clock—This pin provides a serial clock output to the serial ROM.

  • Page 83: Boot Rom Programming Address Register (Csr10-Offset 50H)

    CSR Operation Table 3–53 lists the access rules for the CSR9 register. Table 3–53 CSR9 Register Access Rules Category Description Value after reset FFF483FFH Read access rules — Write access rules — 3.2.2.10 Boot ROM Programming Address Register (CSR10–Offset 50H) The boot ROM programming address register (CSR10) contains the 18-bit boot ROM address.

  • Page 84: General-Purpose Timer Register (Csr11-Offset 58H)

    CSR Operation 3.2.2.11 General-Purpose Timer Register (CSR11–Offset 58H) The general-purpose timer register (CSR11) contains a 16-bit general-purpose timer. It is used mainly by the software driver for timing functions not supplied by the operating system. After this timer is loaded, it starts counting down. The expiration of the timer causes an interrupt in CSR5<11>.

  • Page 85: Sia Status Register (Csr12-Offset 60H)

    CSR Operation Table 3–57 lists the access rules for the CSR11 register. Table 3–57 CSR11 Register Access Rules Category Description Value after reset FFFE0000H Read access rules — Write access rules — 3.2.2.12 SIA Status Register (CSR12–Offset 60H) Figure 3–24 shows the CSR12 register bit fields. Figure 3–24 CSR12 Register Bit Fields 16 15 14 6 5 4 3 2 1 0...
  • Page 86 Otherwise, these bits should be written as 0. TRF—Transmit Remote Fault When set, the 21143 sets bit 13 (remote fault bit) in the transmitted link code words. This can be used to inform the link partner that some fault has occurred.
  • Page 87 TDES0<2>—Link fail TDES0<10>—No carrier TDES0<11>—Loss of carrier The 21143 moves from the link fail state to the link pass state when it receives a legal link pulse stream or two consecutive packets. The driver receives no indication about these packets.

  • Page 88: Sia Connectivity Register (Csr13-Offset 68H)

    Field Description AUI—10BASE-T or AUI When reset, forces the 21143 to select the 10BASE-T interface. When set to 1, forces the 21143 to select the AUI interface. The selection between 10BASE5 (AUI) and 10BASE2 (BNC) is done by CSR15<3>. RST—SIA Reset When reset, resets all the SIA functions and machines.

  • Page 89: Sia Transmit And Receive Register (Csr14-Offset 70H)

    CSR Operation Table 3–61 lists the access rules for the CSR13 register. Table 3–61 CSR13 Register Access Rules Category Description Value after reset FFFF0000H Read access rules If CSR autoconfiguration CSR13<2>) is set, the value of CSR13 reflects the internal states rather than the values written into the CSR.

  • Page 90: Csr14 Register Bit Fields Description

    This bit is meaningful only if CSR14<7> is set. TAS—10BASE-T/AUI Autosensing Enable When set, the 21143 monitors its 10BASE-T and AUI ports. The selected port operation is not affected. See Section 6.2.7. When cleared, the 21143 monitors only the port that is selected for operation AUI or 10BASE-T according to CSR13<3>.
  • Page 91 Note that when port autosensing is enabled, the AUI and 10BASE-T receivers are active simultaneously. ANE—Autonegotiation Enable When set, the 21143 performs an autonegotiation with the link partner to determine the operation mode (Section 6.6). When reset, autonegotiation is disabled. Autonegotiation can be performed only when in 10BASE-T mode.
  • Page 92 TH—10BASE-T Half-Duplex Enable This bit controls the value of bit 5 in the transmitted link code word. When set, the 21143 advertises its ability to also work in half-duplex mode. (Bit 5 in the link code word is set.) When clear, the 21143 advertises that no half-duplex operation is allowed.

  • Page 93: Csr14 Register Access Rules

    CSR Operation Table 3–63 lists the access rules for the CSR14 register. Table 3–63 CSR14 Register Access Rules Category Description Value after reset FFFFFFFFH Read access rules In SIA_auto_configuration mode, a CSR14 read operation reflects internal states, rather than the values written into the CSR.

  • Page 94: Sia And General-Purpose Port Register (Csr15-Offset 78H)

    CSR Operation 3.2.2.15 SIA and General-Purpose Port Register (CSR15–Offset 78H) Figure 3–27 shows the CSR15 register bit fields. CSR15 is divided into two sections: the SIA general register (CSR15<15:0>) and the general-purpose port register (CSR15<31:16>). Appendix E describes the general-purpose port programming procedures.

  • Page 95: Csr15 Register Bit Fields Description

    CSR Operation Table 3–65 describes the bit fields. Table 3–65 CSR15 Register Bit Fields Description (Sheet 1 of 4) Field Description RMI—Receive Match Interrupt Indicates that a received packet has passed address filtering. This bit is cleared when reading CSR15. This bit is not automatically cleared when general purpose port interrupt (CSR5<26>) is cleared.

  • Page 96: Csr15 Register Bit Fields Description

    After a hardware or software reset, the gep<2> function is selected. LGS1—LED/GEP 1 Select This bit selects either the activ or gep<1> function for 21143 pin number 101. When this bit is set, the activ function is selected, which provides an LED indicating receive or transmit activity on the selected port (sets when there is receive or transmit activity on the selected port).
  • Page 97 This is only true for the pins that are configured as output pins. After the 21143 is reset, all gep pins become input pins. If gep<1:0> pins are selected as input pins, an interrupt occurs when either of these bits change state from 1 to 0 or 0 to 1 (provided that the interrupt CSR15<25:24>...

  • Page 98: Sia And Mii Operating Modes

    3.2.2.16 SIA and MII Operating Modes Table 3–67 and Table 3–68 list the programming of the different operating modes in the 21143 using CSR6, CSR13, CSR14, and CSR15. The states of operating mode CSR6<11:10>, full-duplex mode CSR6<9>, and port select CSR6<18> are also identified.

  • Page 99: Programming 10Base-T, Aui, And Bnc Operating Modes

    CSR Operation Table 3–68 is presented here. Table 3–68 Programming 10BASE-T, AUI, and BNC Operating Modes (Sheet 1 of 2) AUI_BNC Mode CSR13 CSR14 CSR15 CSR6<PS,FD> CSR6<OM> Autosensing Disabled, Autonegotiation Disabled 10BASE-T forced 0001 7F3F 0008 High to half-duplex (AUI) 10BASE-T forced 0001 7F3D...
  • Page 100 CSR Operation Table 3–68 Programming 10BASE-T, AUI, and BNC Operating Modes (Sheet 2 of 2) AUI_BNC Mode CSR13 CSR14 CSR15 CSR6<PS,FD> CSR6<OM> Autosensing Disabled, Autonegotiation Enabled 10BASE-T advertising 0001 7FFF 0008 High half- and full-duplex (AUI) 10BASE-T advertising 0001 7FBF 0008 High full-duplex...

  • Page 101: Host Communication

    Descriptor lists and data buffers, described in this chapter. 4.2 Descriptor Lists and Data Buffers The 21143 transfers received data frames to the receive buffers in host memory and transmits data from the transmit buffers in host memory. Descriptors that reside in the host memory act as pointers to these buffers.

  • Page 102: Descriptor Ring And Chain Structure Examples

    Descriptor Lists and Data Buffers A data buffer consists of either an entire frame or part of a frame, but it cannot exceed a single frame. Buffers contain only data; buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers. Data chaining can be enabled or disabled.

  • Page 103: Receive Descriptors

    Descriptor Lists and Data Buffers 4.2.1 Receive Descriptors Figure 4–2 shows the receive descriptor format. Descriptors and receive buffers addresses must be longword aligned. Note: Providing two buffers, two byte-count buffers, and two address pointers in each descriptor enables the adapter port to be compatible with various types of memory- management schemes.

  • Page 104: Receive Descriptor 0 (Rdes0)

    Descriptor Lists and Data Buffers 4.2.1.1 Receive Descriptor 0 (RDES0) RDES0 contains the received frame status, the frame length, and the descriptor ownership information. Figure 4–3 shows the RDES0 bit fields. Figure 4–3 RDES0 Bit Fields 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 OWN - Own Bit FF - Filtering Fail FL - Frame Length...

  • Page 105: Rdes0 Bit Fields Description

    When set, indicates that the descriptor is owned by the 21143. When reset, indicates that the descriptor is owned by the host. The 21143 clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full.
  • Page 106 Indicates the type of frame the buffer contains: 00—Serial received frame. 01—Internal loopback frame. 10—External loopback frame or serial received frame. The 21143 does not differentiate between loopback and serial received frames; therefore, this information is global and reflects only the operating mode (CSR6<11:10>).
  • Page 107 Descriptor Lists and Data Buffers Table 4–1 RDES0 Bit Fields Description (Sheet 3 of 3) Field Description CS—Collision Seen When set, indicates that the frame was damaged by a collision that occurred after the 64 bytes following the start frame delimiter (SFD). This is a late collision. This bit is valid only when last descriptor (RDES0<8>) is set.

  • Page 108: Receive Descriptor 1 (Rdes1)

    RDES1<25> takes precedence over RDES1<24>. 21:11 RBS2—Buffer 2 Size Indicates the size, in bytes, of the second data buffer. If this field is 0, the 21143 ignores this buffer and fetches the next descriptor. The buffer size must be a multiple of 4.

  • Page 109: Receive Descriptor 2 (Rdes2)

    Descriptor Lists and Data Buffers 4.2.1.3 Receive Descriptor 2 (RDES2) Figure 4–5 shows the RDES2 bit field. Figure 4–5 RDES2 Bit Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Buffer Address 1 LJ-04702.WMF Table 4–3 describes the RDES2 bit field.

  • Page 110: Receive Descriptor Status Validity

    Descriptor Lists and Data Buffers 4.2.1.5 Receive Descriptor Status Validity Table 4–5 lists the validity of the receive descriptor status bits in relation to the reception completion status. Table 4–5 Receive Descriptor Status Validity Reception Receive Status Report Status (ES, DE, DT, FS, LS, FL, OF) Overflow Collision after 512 bits...

  • Page 111: Transmit Descriptor 0 (Tdes0)

    Descriptor Lists and Data Buffers Figure 4–7 Transmit Descriptor Format TDES0 Status TDES1 Control Bits Byte-Count Buffer 2 Byte-Count Buffer 1 TDES2 Buffer Address1 TDES3 Buffer Address2 MLO10322.WMF 4.2.2.1 Transmit Descriptor 0 (TDES0) TDES0 contains transmitted frame status and descriptor ownership information. Figure 4–8 shows the TDES0 bit fields.

  • Page 112: Tdes0 Bit Fields Description

    When set, indicates that the descriptor is owned by the 21143. When cleared, indicates that the descriptor is owned by the host. The 21143 clears this bit either when it completes the frame transmission or when the buffers allocated in the descriptor are empty.
  • Page 113 The transmission process enters the suspended state and sets both transmit underflow (CSR5<5>) and transmit interrupt (CSR5<0>). DE—Deferred When set, indicates that the 21143 had to defer while ready to transmit a frame because the carrier was asserted. Host Communication...

  • Page 114: Transmit Descriptor 1 (Tdes1)

    (Sheet 1 of 2) Field Description IC—Interrupt on Completion When set, the 21143 sets transmit interrupt (CSR5<0>) after the present frame has been transmitted. It is valid only when last segment (TDES1<30>) is set or when it is a setup packet. LS—Last Segment When set, indicates that the buffer contains the last segment of a frame.
  • Page 115 This field is not valid if second address chained (TDES1<24>) is set. 10:0 TBS1—Buffer 1 Size Indicates the size, in bytes, of the first data buffer. If this field is 0, the 21143 ignores this buffer and uses buffer 2. Host Communication...

  • Page 116: Filtering Type

    Table 4–8 Filtering Type Description Perfect Filtering The 21143 interprets the descriptor buffer as a setup perfect table of 16 addresses, and sets the 21143 filtering mode to perfect filtering. Hash Filtering The 21143 interprets the descriptor buffer as a setup hash table of 512-bit-plus-one perfect address.

  • Page 117: Transmit Descriptor 2 (Tdes2)

    Descriptor Lists and Data Buffers 4.2.2.3 Transmit Descriptor 2 (TDES2) Figure 4–10 shows the TDES2 bit field. Figure 4–10 TDES2 Bit Field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Buffer Address 1 LJ-04702.WMF Table 4–9 describes the TDES2 bit field.

  • Page 118: Transmit Descriptor Status Validity

    NV—Not valid 4.2.3 Setup Frame A setup frame defines the 21143 Ethernet addresses that are used to filter all incoming frames. The setup frame is never transmitted on the Ethernet wire nor is it looped back to the receive list. When processing the setup frame, the receiver logic temporarily disengages from the Ethernet wire.

  • Page 119: First Setup Frame

    4.2.3.2 Subsequent Setup Frames Subsequent setup frames may be queued to the 21143 despite the reception process state. To ensure correct setup frame processing, these packets may be queued at the beginning of the transmit descriptor’s ring or following a descriptor with a zero- length buffer.

  • Page 120: Perfect Filtering Setup Frame Buffer Format

    Descriptor Lists and Data Buffers Figure 4–12 shows the perfect filtering setup frame buffer format of the addresses. Figure 4–12 Perfect Filtering Setup Frame Buffer Format Physical Address 00 XXXXXXXXXXXXXXXXXXXX <3:0> (Bytes <1:0>) Physical Address 00 XXXXXXXXXXXXXXXXXXXX <7:4> (Bytes <3:2>) Physical Address 00 XXXXXXXXXXXXXXXXXXXX <11:8>...

  • Page 121: Perfect Filtering Buffer

    Descriptor Lists and Data Buffers Example 4–1 shows a perfect filtering setup buffer (fragment). Example 4–1 Perfect Filtering Buffer Ethernet addresses to be filtered: è A8-09-65-12-34-76 09-BC-87-DE-03-15 Setup frame buffer fragment while in little endian byte ordering: ‚ xxxx09A8 xxxx1265 xxxx7634 xxxxBC09 xxxxDE87...

  • Page 122: Imperfect Filtering Setup Frame Buffer

    512-Bit Hash Table 1 Physical Address LJ-04726.WMF The 21143 can store 512 bits serving as hash bucket heads, and one physical 48-bit Ethernet address. Incoming frames with multicast destination addresses are subjected to imperfect filtering. Frames with physical destination addresses are checked against the single physical address.

  • Page 123: Imperfect Filtering Setup Frame Buffer Format

    XXXXXX = Don’t care LJ-04685.WMF Bits are sequentially numbered from right to left and down the hash table. For example, if the CRC (destination address) <8:0> = 33, the 21143 examines bit 1 in the third longword. Host Communication 4–23...

  • Page 124: Imperfect Filtering Buffer

    Descriptor Lists and Data Buffers Example 4–2 shows an imperfect filtering setup frame buffer. Example 4–2 Imperfect Filtering Buffer Ethernet addresses to be filtered: è 25-00-25-00-27-00 A3-C5-62-3F-25-87 D9-C2-C0-99-0B-82 7D-48-4D-FD-CC-0A E7-C1-96-36-89-DD 61-CC-28-55-D3-C7 6B-46-0A-55-2D-7E ‚ A8-12-34-35-76-08 Setup frame buffer while in little endian byte ordering: ƒ...
  • Page 125 Descriptor Lists and Data Buffers Example 4-2 Imperfect Filtering Buffer (Cont.) xxxx0000 xxxx0000 xxxx0040 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx „ xxxx12A8 xxxx3534 xxxx0876 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Setup frame buffer while in big endian byte ordering: …...
  • Page 126 Descriptor Lists and Data Buffers Example 4-2 Imperfect Filtering Buffer (Cont.) 0000xxxx 0000xxxx 0000xxxx 0000xxxx 0000xxxx 0000xxxx 0100xxxx 0000xxxx 0000xxxx 0000xxxx 4000xxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx ò A812xxxx 3435xxxx 7608xxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx è...

  • Page 127: Functional Description

    This section describes the reset commands, interrupt handling, and startup. It also describes the transmit and receive processes. The functional operation of the 21143 is controlled by the driver interface located in the host communication area. The driver interface activity is controlled by control and status registers (CSRs), descriptor lists, and data buffers.

  • Page 128: Power-Saving Modes

    After either a hardware or software reset command, the first bus transaction to the 21143 should not be initiated for at least 50 PCI clock cycles. When the reset sequence completes, the 21143 can accept host commands. The receive and transmit processes are placed in the stopped state (Table 4–13 and Table 4–14).

  • Page 129: Snooze Power-Saving Mode

    Functional Description 4.3.2.2 Snooze Power-Saving Mode Snooze mode is a dynamic power-saving mode. When the snooze mode bit (CFDD<30>) is set, the 21143 reduces its power dissipation unless one or more of the following conditions is true: • PCI slave or master access is conducted.

  • Page 130: Arbitration Scheme

    Functional Description 4.3.3 Arbitration Scheme The arbitration scheme is used by the 21143 to grant precedence to the receive process instead of the transmit process (CSR0<1>). The technical expressions used in this table are described in the following list: •...

  • Page 131: Arbitration Scheme

    Functional Description Table 4–12 lists a description of the arbitration scheme. Table 4–12 Arbitration Scheme Txreq Rxreq TxEN RxF<thrx TxF<thtx Chosen Process — — — — — — — — Receive process — — Receive process — — Transmit process —...

  • Page 132: Interrupts

    (CSR5<6>) indicates that one or more received frames were delivered to host memory. The driver must scan all descriptors, from the last recorded position to the first one owned by the 21143. An interrupt is generated only once for simultaneous, multiple interrupting events.

  • Page 133: Startup Procedure

    1. Wait 50 PCI clock cycles for the 21143 to complete its reset sequence. 2. Update configuration registers (Section 3.1): a. Read the configuration ID and revision registers to identify the 21143 and its revision. b. Write the configuration interrupt register (if interrupt mapping is necessary).

  • Page 134: Descriptor Acquisition

    When start/stop receive (CSR6<1>) sets immediately after being placed in the running state. • When the 21143 begins writing frame data to a data buffer pointed to by the current descriptor, and the buffer ends before the frame ends. •...
  • Page 135 While waiting for the PCI bus, the 21143 continues to receive and store the data in the FIFO. After receiving the PCI bus, the 21143 sets first descriptor (RDES0<9>), to delimit the frame.

  • Page 136: Receive Process State Transitions

    Running Memory or host bus parity Running The 21143 operation is stopped and fatal error encountered. bus error (CSR5<13>) sets. The 21143 remains in the running state. A software reset must be issued to release the 21143.

  • Page 137: Transmit Process

    If TDES1<30> is set, it indicates the last buffer of the frame. After the last buffer of the frame has been transmitted, the 21143 writes back the final status information to the transmit descriptor 0 (TDES0) word of the descriptor that has the last segment set in transmit descriptor 1 TDES1<30>).

  • Page 138: Transmit Polling Suspended

    Transmit polling can be suspended by either of the following conditions: • The 21143 detects a descriptor owned by the host (TDES0<31>=0). To resume, the driver must give descriptor ownership to the 21143 and then issue a poll demand command. •...
  • Page 139 Running Parity error detected by Running Transmission is cut off and fatal bus memory or host bus. error (CSR5<13>) is set. The 21143 remains in the running state. If a software reset occurs, normal operation continues. Host Communication 4–39...
  • Page 140 Functional Description Table 4–14 Transmit Process State Transitions (Sheet 2 of 2) From State Event To State Action Running Reset command. Stopped Transmission is cut off. If CSR4 was not changed, the position in the list is retained. If CSR4 was changed, the next descriptor address is fetched from the header list (CSR4) when the poll demand command is issued.

  • Page 141: Host Bus Operation

    21143 uses the PCI bus to communicate with the host CPU and memory. The 21143 is directly compatible with revision 2.0 and revision 2.1 of the PCI Local Bus Specification. The 21143 supports a subset of the PCI-bus cycles (transactions).

  • Page 142: Bus Commands

    Master support for this command is controlled by (CSR0<21> 5.3 Bus Slave Operation All host accesses to CSRs and configuration registers in the 21143 are executed with the 21143 acting as the slave. The bus slave can perform the following operations: •...

  • Page 143: Slave Read Cycle (I/O Or Memory Target)

    3. The host deasserts frame_l signal and asserts irdy_l signal. 4. The 21143 asserts devsel_l, and, at the next cycle, drives the data on the ad lines. 5. The read transaction completes when both irdy_l and trdy_l are asserted by the host and the 21143, respectively, on the same clock edge.

  • Page 144: Slave Write Cycle (I/O Or Memory Target)

    (slave write operation) on the c_be_l lines. 2. The 21143 samples the address and the bus command on the next clock edge. 3. The host deasserts frame_l and drives the data on the ad lines along with irdy_l.

  • Page 145: Configuration Read And Write Cycles

    LJ-04742.WMF 5.3.3 Configuration Read and Write Cycles The 21143 provides a way for software to analyze and configure the system before defining any address assignments or mapping. The 21143 provides 256 bytes of configuration registers. Section 3.1 describes these registers.

  • Page 146: Bus Master Operation

    LJ-04743.WMF 5.4 Bus Master Operation All memory accesses are completed with the 21143 as the master on the PCI bus. The bus master can perform the following operations: • Bus arbitration • Memory read cycle •...

  • Page 147: Bus Arbitration

    2. The arbiter, in response, asserts gnt_l (gnt_l can be deasserted on any clock). 3. The 21143 ensures that its gnt_l is asserted on the clock edge that it wants to drive frame_l. (If gnt_l is deasserted, the 21143 does not proceed.) 4.

  • Page 148: Memory Read Cycle

    The 21143 drives 0000 on the c_be_l lines (longword access). 5. The memory controller drives the data on the ad lines and asserts trdy_l. 6. The 21143 samples the data on each rising clock edge when both irdy_l and trdy_l are asserted.

  • Page 149: Memory Write Cycle

    2. The 21143 asserts irdy_l until the end of the transaction and drives the data on the ad lines. 3. The memory controller samples the address and the bus command on the next clock edge and asserts devsel_l.

  • Page 150: Termination Cycles

    Termination cycles can be initiated during either slave or master cycles. 5.5.1 Slave-Initiated Termination A slave-initiated termination can occur when the 21143 operates as a slave device on the PCI bus. A slave can initiated the following types of terminations:...

  • Page 151: Disconnect Termination

    The 21143 initiates disconnect termination in slave mode when it is accessed by the host with I/O or memory burst cycles. The 21143 asserts stop_l to request the host to terminate the transaction. After stop_l is asserted, it remains asserted until frame_l is deasserted.

  • Page 152: Retry Termination

    The 21143 configuration registers CSID and CCIS are accessed by the host, before their contents are loaded from the serial ROM. The 21143 does not assert trdy_l in response to these host accesses. It asserts stop_l requesting that the host terminate the transaction. Signal stop_l remains asserted until irdy_l is deasserted.

  • Page 153: Master-Initiated Termination

    Termination Cycles 5.5.2 Master-Initiated Termination A master-initiated termination can occur when the 21143 operates as a master device on the PCI bus. Terminations can be issued by either the 21143 or the memory controller. The 21143 can perform the following terminations:...

  • Page 154: Normal Completion

    If the target does not assert devsel_l within five cycles from the assertion of frame_l, the 21143 performs a normal completion. It then releases the bus and asserts both master abort (CFCS<29>) and fatal bus error (CSR5<13>). Figure 5–10 shows the 21143 master abort termination.

  • Page 155: Memory-Controller-Initiated Termination

    LJ-04735.WMF 5.5.2.2 Memory-Controller-Initiated Termination The memory controller or target can initiate certain terminations when the 21143 is the bus master. Target Abort The 21143 aborts the bus transaction when the target asserts stop_l and deasserts devsel_l. This indicates that the target wants the transaction to be aborted. The 21143 releases the bus and asserts both received target abort (CFCS<28>) and fatal...

  • Page 156: Target Abort

    Target Disconnect Termination The 21143 terminates the bus transaction when the target asserts stop_l, which remains asserted until frame_l is deasserted. The 21143 releases the bus. Then, it retries at least the last data transaction after regaining the bus in another arbitration.

  • Page 157: Target Disconnect

    LJ-04732.WMF Target Retry The 21143 retries the bus transaction when the target asserts stop_l and deasserts trdy_l; stop_l remains asserted until frame_l is deasserted. The 21143 releases the bus. Then, it retries at least the last two data transactions after regaining the bus in another arbitration.

  • Page 158: Parity

    (1 or 0) on all the ad and c_be_l lines. If a data parity error is detected or perr_l is asserted when the 21143 is a bus master, the 21143 asserts data parity report (CFCS<24>) and fatal bus error (CSR5<13>).

  • Page 159: Parking

    LJ-04736.WMF 5.7 Parking Parking in the PCI bus allows the central arbiter to pause any selected agent. The 21143 enters the parking state when the arbiter asserts its gnt_l line while the bus is idle. Host Bus Operation 5–19...

  • Page 161: Network Interface Operation

    Network Interface Operation This chapter describes the operation of the MII/SYM port, the 10BASE-T port, and the AUI port. It also describes media access control (MAC), loopback, and full- duplex operations. Appendix D describes the port selection procedure. 6.1 MII/SYM Port This section provides a description of the 100BASE-T terminology, the interface, the signals used, and the operating modes.

  • Page 162: Interface Description

    MII/SYM Port • 100BASE-TX refers to the IEEE 802.3 PHY layer, which includes the 100BASE-X PCS and PMA together with the physical layer medium dependent (PMD). It uses UTP category 5 (CAT5) cables and STP cables. • 100BASE-FX refers to the IEEE 802.3 PHY layer, which includes the 100BASE-X PCS and PMA together with the PMD.
  • Page 163 MDIO Management data input/output is used to transfer control signals between the 21143 and the PHY chip. The 21143 is capable of initiating the transfer of control signals to and from the PHY device by using this line. mii/sym_rclk RX_CLK Receive clock synchronizes all receive signals.

  • Page 164: Operating Modes

    MII 10-Mb/s mode—The 21143 implements the MII with a data rate of 10 Mb/s and both the receive clock mii/sym_rclk and the transmit clock mii/sym_tclk operate at 2.5 MHz. In this mode, the 21143 can be used with any device that implements the 10-Mb/s PHY layer and an MII.

  • Page 165: 10Base-T And Aui Functions

    10BASE-T and AUI Functions – 4-bit and 5-bit decoding and encoding – SSD and ESD detection and generation – Bit alignment – Carrier detect – Collision detect – Symbol error detection – Link timer This mode enables a direct interface with existing FDDI TP-PMD devices that implement the physical functions.

  • Page 166: Receivers And Drivers

    2. An external clock generator module connected to xtal1; xtal2 remains uncon- nected. In both cases, the 21143 must be provided with a 20-MHz signal that is internally divided by 2 to generate the 10-MHz clock. When driving the oscillator from an external clock source, an external clock having the following characteristics must be used to ensure proper operation of the 21143: •...

  • Page 167: Smart Squelch

    MAC layer accordingly. To detect polarity, the 21143 uses the link test pulse and the end-of-frame delimiter in an algorithm integrated into the link integrity test, as specified in the IEEE 802.3 10BASE-T supplement.

  • Page 168: Network Port Autosensing

    10BASE-T and AUI Functions 6.2.7 Network Port Autosensing The 21143 can sense the AUI and 10BASE-T ports at the same time. In addition, while the AUI port is used for transmission, it can also send the 10BASE-T link pulses onto the TP wires. These features, along with reported status bits and...

  • Page 169: 10Base-T Link Integrity Test

    A broken or noisy wire can bring the 21143 back to the link fail state. It will then report the wire failure by generating a link fail interrupt to the host and will immediately stop the receive and transmit paths.

  • Page 170: Ethernet And Ieee 802.3 Frames

    Media Access Control Operation 6.3.1.1 Ethernet and IEEE 802.3 Frames Ethernet is the generic name for the network type. An Ethernet frame has a minimum length of 64 bytes and a maximum length of 1518 bytes, exclusive of the preamble and the start frame delimiter.

  • Page 171: Frame Format Table

    A data field shorter than 46 bytes, which is specified by the length field, is allowed. Unless padding is disabled (TDES1<23>), it is added by the 21143 when transmitting to fill the data field up to 46 bytes.

  • Page 172: Ethernet Reception Addressing

    Media Access Control Operation 6.3.2 Ethernet Reception Addressing The 21143 can be set up to recognize any one of the Ethernet receive address groups described in Table 6–5. Each group is separate and distinct from the other groups. Table 6–5 Ethernet Receive Address Groups...

  • Page 173: Detailed Transmit Operation

    21143 to take it. After the 21143 has been notified of this transmit list, the 21143 starts to move the data bytes from the host memory to the internal transmit FIFO.

  • Page 174: Frame Encapsulation

    The IPG time is divided into two parts: IPS1 and IPS2. 1. IPS1 time (60-bit time): the 21143 monitors the network for an idle state. If a carrier is sensed on the serial line during this time, the 21143 defers and waits until the line is idle again before restarting the IPS1 time count.

  • Page 175: Collision

    When 16 attempts have been made at transmission and all have been terminated by a collision, the 21143 sets an error status bit in the descriptor (TDES0<8>) and, if enabled, issues a normal transmit termination (CSR5<0>) interrupt to the host.

  • Page 176: Transmit Parameter Values

    Status information is written into CSR5 if an error occurs during the operation of the transmit machine itself. If a normal interrupt summary (CSR7<16>) is enabled, the 21143 issues a normal transmit termination interrupt (CSR5<0>) to the host.

  • Page 177: Detailed Receive Operation

    The 21143 continuously monitors the network when reception is enabled. When activity is recognized, it starts to process the incoming data. After detecting receive activity on the line, the 21143 starts to process the preamble bytes based on the mode of operation.

  • Page 178: 100Base-Tx Or 100Base-Fx Mode Preambles

    10BASE-T or AUI mode or 6 bits in MII/SYM mode) or a 00 (everywhere), the reception of the current frame is aborted. The frame is not received, and the 21143 waits until the network activity stops (Section 6.3.4.1) before monitoring the network activity for a new preamble.

  • Page 179: Frame Decapsulation

    The 21143 checks the CRC bytes of all received frames before releasing them to the host processor. When operating in either 100BASE-TX or 100BASE-FX mode, the 21143 also checks that the frame ends with the TR symbol pair; if not, the 21143 reports a CRC error in the packet reception status.

  • Page 180: Frame Reception Status

    When reception terminates, the 21143 determines the status of the received frame and loads it into the receive status word in the buffer descriptor. An interrupt is issued if enabled. The 21143 may report the following conditions at the end of frame reception: •...

  • Page 181: Loopback Operations

    Internal loopback mode also supports the following modes of operation: 1. Media access control (MAC) internal loopback mode in which transmit packets are looped back at the MAC level and the 21143 disengages the SIA. The loop- back data rate is 10 Mb/s, or 10/100 Mb/s in MII/SYM mode.

  • Page 182: External Loopback Mode

    Ethernet cable function correctly. In external loopback mode, the 21143 takes frames from the transmit list and transmits them on the Ethernet wire. Concurrently, the 21143 listens to the line that carries its own transmissions and places incoming frames in the receive list.

  • Page 183: Driver Restoring Normal Operation

    2. Prepare the appropriate transmit and receive descriptor lists in host memory. These lists can follow the existing lists at the point of suspension or be new lists identified to the 21143 by the receive list base address in CSR3 and by the trans- mit list address in CSR4.

  • Page 184: Full-Duplex Operation

    21143 by referencing the receive list base address in CSR3 and the transmit list base address in CSR4.

  • Page 185: Autonegotiation

    The 21143 implements this algorithm for 10BASE-T and 100BASE-TX half-duplex and full-duplex mode autonegotiation and 100BASE-T4 mode autonegotiation. The whole negotiation is done by the 21143 without software involvement. At the end of the negotiation, the 21143 chooses the operating mode according to Table 6–8.

  • Page 186: Capture Effect-A Value-Added Feature

    Before enabling its receive or transmit paths, or after the link integrity test has failed, the 21143 starts an autonegotiation sequence with its link partner. The 21143 stops sending its link pulses for at least 1 second and moves its link partner into the link fail state, forcing it to renegotiate.
  • Page 187 Capture Effect–A Value-Added Feature 2. The stations experience a collision. Both stations increment their collision count to 1. 3. Each station picks a backoff time value that is uniformly distributed from 0 to (2n)–1 slots. In this example, station B selects a backoff of 1 (a 50% probabil- ity), and station A selects a backoff of 0.

  • Page 188: Capture-Effect Sequence

    Backoff 0, 1, 2, ... 7 6.7.2 Resolving Capture Effect The 21143 generally resolves the capture effect by having the station use, after a successful transmission of a frame by a station, a 2–0 backoff algorithm on the next transmit frame. If the station senses a frame on the network before it attempts to transmit the next frame, regardless of whether the sensed frame destination address matches the station’s source address, the station returns to use the standard truncated...

  • Page 189: Enhanced Resolution For Capture Effect

    (n=1, where n is the retransmission attempts), the 21143 stops its backoff timer for the duration when the channel is busy. It continues its backoff timer when the channel is idle. For any other collision cases, the backoff timer is not stopped.

  • Page 191: External Ports

    ROM port. 7.1 Overview The 21143 provides a boot ROM interface that may be optionally used on the adapter. The boot ROM (expansion ROM) may contain code that can be executed for device-specific initialization and, possibly, a system boot function.

  • Page 192: Boot Rom, Serial Rom, And External Register Connection

    Boot ROM and Serial ROM Connection Figure 7–1 Boot ROM, Serial ROM, and External Register Connection External 21143 Register Logic br_ad<7:0> data<7:0> EEPROM/Flash in<8> in<7:0> Latch out<8> out<7:0> add<15:8> add<16> in<8> in<7:0> Latch out<8> out<7:2> <1> <0> we_l oe_l add<7:2>...

  • Page 193: Boot Rom Operations

    6. In response, the boot ROM drives the data on the br_ad lines. 7. The 21143 terminates the byte read cycle by sampling the data, by placing it in CSR9<7:0>, and by deasserting the br_ce_l signal.

  • Page 194: Byte Write

    CSR10, setting a write command in CSR9 (CSR9<13> and CSR9<12> = 1), and by writing the data to CSR9<7:0>. 2. The 21143 drives the boot ROM address bits <7:2> and the signals oe_l and we_l on the br_ad lines, drives address bit 17 on the br_a<0> line, and sets br_a<1>.

  • Page 195: Dword Read

    21143 takes the following steps: 1. The 21143 drives the boot ROM address bits <7:2> and the control signals oe_l and we_l on the br_ad lines, drives address bit 17 on the br_a<0> line, and sets br_a<1>.

  • Page 196: Boot Rom Dword Read Cycle

    14. In response, the boot ROM drives the data on the br_ad lines (byte 0). 15. The 21143 samples the data and deasserts the br_ce_l signal. 16. The 21143 assembles the 4 bytes, drives the data on the ad lines, and asserts trdy_l.

  • Page 197: Serial Rom Operations

    All EEPROM access sequences and timing are handled by software. An exception to this is the loading of the CSID and CCIS configuration register values from the SROM. This read is automatically completed by the 21143 after a hardware reset without software involvement.

  • Page 198: Read Cycle

    Serial ROM Operations Figure 7–5 Read Cycle (Page 1 of 2) Write CSR9<2:0> = 000#2 30 ns Write CSR9<2:0> = 001#2 50 ns Write CSR9<2:0> = 011#2 250 ns Write CSR9<2:0> = 001#2 100 ns Write CSR9<2:0> = 101#2 150 ns Write CSR9<2:0>...

  • Page 199: Read Cycle

    Serial ROM Operations Figure 7–6 Read Cycle (Page 2 of 2) Write CSR9<2:0> = 011#2 100 ns Read CSR9<3> = DX 150 ns DX = Current Data Bit Write CSR9<2:0> = 001#2 250 ns Data DX = D0 ? Write CSR9<2:0> = 000#2 Wait 100 ns Until Ready LJ-04050.WMF External Ports...

  • Page 200: Write Operation

    Serial ROM Operations Figure 7–7 shows the read operation timing of the address and data. Figure 7–7 Read Operation Dout LJ-03994.WMF 7.4.2 Write Operation Write operations consist of three phases: 1. Command phase—3 bits (binary code of 101 2. Address phase—6 bits for 256-bit to 1Kb ROMs, 8 bits for 2Kb to 4Kb ROMs. 3.

  • Page 201: Write Cycle

    Serial ROM Operations Figure 7–8 Write Cycle (Page 1 of 2) Write CSR9<2:0> = 000#2 30 ns Write CSR9<2:0> = 001#2 50 ns Write CSR9<2:0> = 011#2 250 ns Write CSR9<2:0> = 001#2 100 ns Write CSR9<2:0> = 101#2 150 ns Write CSR9<2:0>...

  • Page 202: Write Cycle

    Serial ROM Operations Figure 7–9 Write Cycle (Page 2 of 2) Write CSR9<2:0> = DX01#2 150 ns Write CSR9<2:0> = DX11#2 250 ns DX = Current Data Bit Write CSR9<2:0> = DX01#2 100 ns Data DX = D0? Write CSR9<2:0> = 000#2 250 ns Write CSR9<2:0>...

  • Page 203: External Register Operation

    Section 7.3.1. The only differences are that now the 21143 drives 1 on both the we_l and oe_l boot ROM inputs and drives 0 on br_a<0>. This, together with the assertion of br_ce_l, performs the actual read operation. The data is sampled by the 21143 and is placed in CSR9<7:0>.

  • Page 204: Led Description

    CSR9<7:0>. The 21143 performs the same steps as described in Section 7.3.2. The only differences are that now the 21143 drives 1 on both the we_l and oe_l boot ROM inputs and drives 1 on br_a<0>. This, together with the assertion of br_ce_l, performs the actual write operation.

  • Page 205: Remotely Waking Up The Lan

    The 21143 performs no network activities while in the remote wake-up-LAN mode of operation—it only monitors the network for receipt of a Magic Packet. If a Magic Packet is addressed to the 21143 on the network, the 21143 asserts (low) an interrupt pin (int_l) and sets (high) a special output pin (gep<2>)

  • Page 206: Remote Wake-Up Controller Block Diagram

    Remote Wake-Up Controller Block Diagram • SecureON—Enables a password-security feature that can be added to the Magic Packet and an attack-limiter circuit for limiting the number of invalid passwords. Figure 8–1 21143 Remote Wake-Up Controller Block Diagram Board Boot ROM/ Control...

  • Page 207: Remote Wake-Up-Lan Operation

    The 21143 continually senses the main system power status on a single dedicated pin. When the 21143 notices that the main system power has been turned off, it automatically enters remote wake-up-LAN mode. Also, if the auxiliary power supply goes off and then returns (with the main power still off), the 21143 will automatically enter remote wake-up-LAN mode.

  • Page 208: Remote Wake-Up-Lan Mode With Main System Power On

    FORCE_WAKE_UP_LAN (FWUL) bit in the 21143’s configuration wake-up command register (see Section 8.7.3). When this bit is set, the 21143 is forced to enter remote wake-up-LAN mode and read the remote wake-up-LAN data block from the SROM. If it detects bad CRC for the block, the 21143 ignores its remote wake-up-LAN functions.

  • Page 209: Invalid Password Limiter

    The system recognizes the assertion of these pins as a wake-up call. The 21143 also provides a register status bit that indicates receipt of a Magic Packet. This register bit will not be cleared by any reset (write 1 to clear the bit).

  • Page 210: Cfrv Register Bit Fields

    Indicates the 21143 revision number and is equal to 3H. This number is incremented for subsequent 21143 revisions. Step Number Indicates the 21143 step number and is equal to 0H. This number is incremented for subsequent 21143 steps within the current revision. Table 8–2 lists the access rules for the CFRV register.

  • Page 211: Sia And General-Purpose Port Register (Csr15-Offset 78H)

    SIA and General-Purpose Port Register (CSR15–Offset 78H) 8.6 SIA and General-Purpose Port Register (CSR15–Offset 78H) This section shows and describes the enhanced format of CSR15, which includes the addition of bit 15 (HCKR) and bit 14 (RMP). Figure 8–3 shows the CSR15 register bit fields. CSR15 is divided into two sections: the SIA general register (CSR15<15:0>) and the general-purpose port register (CSR15<31:16>).
  • Page 212 SIA and General-Purpose Port Register (CSR15–Offset 78H) Table 8–3 describes the bit fields. Table 8–3 CSR15 Register Bit Fields Description (Sheet 1 of 4) Field Description RMI—Receive Match Interrupt Indicates that a packet has passed address filtering. This bit is cleared when reading CSR15. This bit is not automatically cleared when general-purpose port interrupt (CSR5<26>) is cleared.
  • Page 213 After a hardware or software reset, the gep<2> function is selected. LGS1—LED/GEP 1 Select This bit selects either the activ or gep<1> function for 21143 pin number 101. When this bit is set, the activ function is selected, which provides a LED indicating receive or transmit activity on the selected port (sets when there is receive or transmit activity on the selected port).
  • Page 214 This is only true for the pins that are configured as output pins. After the 21143 is reset, all gep pins become input pins. If gep<1:0> pins are selected as input pins, an interrupt occurs when either of these bits change state from 1 to 0 or 0 to 1 (provided that the interrupt CSR15<25:24>...

  • Page 215: Pci Configuration Registers

    8.7 PCI Configuration Registers The 21143 contains five configuration registers in addition to those registers listed in Table 3–1. The Ethernet address and the SecureON password registers use a naming convention of A-B-C-D-E-F, with “A” representing the first byte of the remote wake-up-LAN IEEE address to be transmitted on the Ethernet wire (see Section 8.9).

  • Page 216: Configuration Wake-Up-Lan Ieee Address 0 Register

    ROM. If the CWUA0 is accessed by the host before the remote wake-up- LAN IEEE parameters are loaded from the serial ROM, the 21143 responds with a retry termination on the PCI bus. Figure 8–4 shows the CWUA0 register.

  • Page 217: Cwua0 Register Bit Fields

    PCI Configuration Registers Figure 8–4 CWUA0 Register Bit Fields Remote Wake-Up-LAN IEEE Address D <23:16> Remote Wake-Up-LAN IEEE Address C <31:24> Remote Wake-Up-LAN IEEE Address B <39:32> Remote Wake-Up-LAN IEEE Address A <47:40> FM-05977.AI4 Table 8–7 describes the CWUA0 register bit fields. Table 8–7 CWUA0 Register Bit Fields Description Field Description...

  • Page 218: Configuration Wake-Up-Lan Ieee Address 1 Register

    ROM. If the CWUA1 is accessed by the host before the remote wake-up- LAN IEEE parameters are loaded from the serial ROM, the 21143 responds with a retry termination on the PCI bus. Figure 8–5 shows the CWUA1 register.

  • Page 219: Configuration Wake-Up Command Register (Cwuc-Offset 54H)

    ROM. If the CWUC is accessed by the host before the remote wake-up-LAN parameters are loaded from the serial ROM, the 21143 responds with a retry termination on the PCI bus. Figure 8–6 shows the CWUC register.
  • Page 220 The remote wake-up-LAN mode attempts autosensing on the SYM PHY port and enables autonegotiation MII Ability When set, indicates that the 21143 is connected to an MII PHY device. The remote wake-up-LAN mode selects the MII PHY port. TP10 Ability When set, indicates that the 21143 is connected to the twisted pairs.

  • Page 221: Secureon™ Password Register (Sop0-Offset 4Ch)

    If the SOP0 is accessed by the host before the remote wake-up-LAN parameters are loaded from the serial ROM, the 21143 responds with a retry termination on the PCI bus. Figure 8–7 shows the SOP0 register.

  • Page 222: Secureon Password Register (Sop1-Offset 50H)

    If the SOP1 is accessed by the host before the remote wake-up-LAN parameters are loaded from the serial ROM, the 21143 responds with a retry termination on the PCI bus. Figure 8–8 shows the SOP1 register.

  • Page 223: Sop1 Register Bit Fields

    PCI Configuration Registers Figure 8–8 SOP1 Register Bit Fields SecureON Password F <7:0> SecureON Password E <15:8> FM-05978.AI4 Table 8–15 describes the SOP1 register bit fields. Table 8–15 SOP1 Register Bit Fields Description Field Description 15:8 SecureON Password F <7:0> Defines one byte of the SecureON password.

  • Page 224: Remote Wake-Up-Lan Data Block In The Srom

    Remote Wake-Up-LAN Data Block in the SROM 8.8 Remote Wake-Up-LAN Data Block in the SROM Table 8–17 shows the remote wake-up-LAN data block in the SROM. Table 8–17 Data Block in the SROM Byte Offset SROM Application-Specific SROM Data SecureON Password SecureON Password SecureON Password SecureON Password...

  • Page 225: Remote Wake-Up-Lan Ieee Address And Command (Srom)

    Remote Wake-Up-LAN Data Block in the SROM 8.8.1 Remote Wake-Up-LAN IEEE Address and Command (SROM) Table 8–18 describes the fields for the SecureON password, the remote wake-up- LAN IEEE address, and the remote wake-up-LAN command in the SROM. Table 8–18 Remote Wake-Up-LAN Data Block in the SROM (Sheet 1 of 3) Size Field...
  • Page 226 1s. • Remote wake-up-LAN IEEE address register and SecureON password register are disabled for writes. The 21143 exits from the Lock state only in a hardware reset. When set, indicates that the 21143 is connected to a symbol PHY device.
  • Page 227 Remote Wake-Up-LAN Data Block in the SROM Table 8–18 Remote Wake-Up-LAN Data Block in the SROM (Sheet 3 of 3) Size Field (Bytes) Description remote wake-up-LAN WAKE_UP_ The CRC polynomial for the block is calculated LAN_BLOCK_ on bytes 96:127 as follows: FCS(X) = X + 1.

  • Page 228: 21143 Magic Packet Format

    21143 Magic Packet Format 8.9 21143 Magic Packet Format Table 8–19 shows the structure of a Magic Packet used in the 21143. Table 8–19 Magic Packet Format for the 21143 Physical/Broadcast Destination Address (A) Physical/Broadcast Destination Address (B) Physical/Broadcast Destination Address (C)

  • Page 229: Magic Packet Fields

    21143 Magic Packet Format Example 8–1 shows the fields of a 21143 Magic Packet with a valid SecureON password. Example 8–1 21143 Magic Packet Fields Physical Destination Address (A-B-C-D-E-F) 08-00-2B-11-22-33 Source Node Physical Address 08-00-2B-44-55-66 Length/Type 00-00 SecureON Password (A-B-C-D-E-F) E1-E2-E3-E4-E5-E6...

  • Page 231: Joint Test Action Group-Test Logic

    JTAG test logic supports testing, observing, and modifying circuit activity during the components normal operation. As a PCI device, the 21143 supports the IEEE standard 1149.1 Test Access Port and Boundary Scan Architecture. The IEEE 1149.1 standard specifies the rules and permissions that govern the design of the 21143 JTAG test logic support.

  • Page 232: Registers

    In this application, the 21143 receives the same tck and tms signals as the other devices. The entire 1149.1 ring is connected to either a motherboard test connector for test purposes or to a resident 1149.1 controller.

  • Page 233: Bypass Register

    The bypass register is a 1-bit shift register that provides a single-bit serial connection between the tdi and tdo signals when either no other test data register in the 21143 JTAG test logic registers is selected, or the test logic in the 21143 JTAG is bypassed.

  • Page 234: A.2.4 Test Access Port Controller

    The TAP controller generates clocks and control signals to control the operation of the test logic. The TAP controller consists of a state machine and control dispatch logic. The 21143 fully implements the TAP state machine as described in the IEEE P1149.1 standard.

  • Page 235: Dna Csma/Cd Counters And Events Support

    DNA CSMA/CD Counters and Events Support This appendix describes the 21143 features that support the driver when implementing and reporting the specified counters and events . CSMA/CD specified events can be reported by the driver based on these features. B.1 CSMA/CD Counters Table B–1 lists the counters and features.

  • Page 236: Csma/Cd Counters

    CSMA/CD Counters (Sheet 2 of 3) Table B–1 CSMA/CD Counters Counter 21143 Feature Frames sent, initially deferred Driver must count the successfully transmitted frames when deferred (TDES0<0>) is set. Frames sent, single collision Driver must count the successfully transmitted frames when the collision count (TDES0<6:3>) is equal to 1.
  • Page 237 CSMA/CD Counters Table B–1 CSMA/CD Counters (Sheet 3 of 3) Counter 21143 Feature System buffer unavailable Reported in the missed frame counter CSR8<15:0> (Section 3.2.2.8). User buffer unavailable Maintained by the driver. Collision detect check failed Driver must count the transmit descriptors when heartbeat fail (TDES0<7>) is set.

  • Page 239: Hash C Routine

    Hash C Routine This appendix provides examples of a C routine that generates the hash index for a given Ethernet address. The bit position in the hash table is taken from the CRC32 checksum derived from the first 6 bytes. There are two C routines that follow: the first is for the little endian architecture and the second is for big endian architecture.

  • Page 240: Big Endian Architecture Hash C Routine

    Big Endian Architecture Hash C Routine main (int argc, char *argv[]) { int Index; char m[6]; if (argc < 2) { printf(“usage: hash xx-xx-xx-xx-xx-xx\n”); return; sscanf(argv[1],”%2X-%2X-%2X-%2X-%2X-%2X”, &m[0],&m[1],&m[2], &m[3],&m[4],&m[5]); Index = HashIndex(&m[0]); printf(“hash_index = %d byte: %d bit: %d\n”, Index,Index/8,Index%8); unsigned HashIndex (char *Address) { unsigned Crc = 0xffffffff;...
  • Page 241 Big Endian Architecture Hash C Routine /* the hash index is given by the upper 9 bits of the CRC * taken in decreasing order of significance * index<0> = crc<31> * index<1> = crc<30> * ... * index<9> = crc<23> for (Index=0, Bit=23, Shift=8;...

  • Page 243: Port Selection Procedure

    Port Selection Procedure This appendix describes the port selection procedure for selecting one of the following 21143 ports: 10BASE-T These procedures provide the values to which the CSRs should be programmed, and also the order of programming. These procedures are for mode programming after reset, not for changing modes during operation.

  • Page 244: Sym Port Selection

    SYM Port Selection D.2 SYM Port Selection This section describes SYM port selection for both half-duplex and full-duplex modes. • Half-duplex mode CSR6<18> = 0 CSR13 = 0000H CSR14 = 0000H CSR6<18> = 1, CSR6<23> = 1, CSR6<24> = 1 •...

  • Page 245: Aui Port Selection

    AUI Port Selection D.4 AUI Port Selection This section describes the AUI port selection for both 10BASE5 and 10BASE2 modes. • 10BASE5 (AUI) mode CSR6<18> = 0 CSR13 = 0000H CSR14 = 0705H CSR15<3> = 1 CSR13 = 0009H • 10BASE2 (BNC) mode CSR6<18>...

  • Page 247: General-Purpose Port And Led Programming

    LED/Control The procedures provide the CSR15 values for programming each of these functions. It uses 21143 pin 103 (gep<1>/activ) as an example. The CSR values provided in each line should be written in one CSR access. E.1 Input Port Selection with Interrupt To select the input port with the interrupt function, write the following values: First write CSR15<27>...

  • Page 248: Output Port Selection

    Output Port Selection E.3 Output Port Selection To select the output port function, write the following values: First write CSR15<27> = 1, CSR15<21> = 0, CSR15<17> = 1 Then write CSR15<27> = 0. E.4 LED/Control Selection To select the LED/Control function, write the following values: First write CSR15<27>...

  • Page 249: Support, Products, And Documentation

    Support, Products, and Documentation If you need technical support, a Digital Semiconductor Product Catalog, or help deciding which documentation best meets your needs, visit the Digital Semiconductor World Wide Web Internet site: http://www.digital.com/semiconductor You can also call the Digital Semiconductor Information Line or the Digital Semiconductor Customer Technology Center.
  • Page 250 Digital Semiconductor Products To order the Digital Semiconductor 21143 10/100-Mb/s Ethernet LAN Controller and for more information about an Evaluation Board kit, contact your local distributor. The following tables list some of the semiconductor products available from Digital Semiconductor. Chips...
  • Page 251 Title Order Number Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller EC–QN7MB–TE Product Brief Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller Data EC–QN7PC–TE Sheet Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller EC–QN7NC–TE Hardware Reference Manual Third–Party Documentation You can order the following third-party documentation directly from the vendor. Title Vendor PCI Local Bus Specification, Revision 2.1...
  • Page 253 Index Numerics 100BASE-FX Boot ROM implementation 6–2 byte read 7–3 100BASE-T byte write 7–4 Dword read 7–5 definition 6–1 interface 3–46 100BASE-T4 overview 7–1 implementation 6–1 pointer 3–49 100BASE-TX select 3–48 implementation 6–2 Boot ROM programming address register 100BASE-X See CSR10 implementation 6–1 Boot ROM, serial ROM, and MII management...
  • Page 254 Carrier-sense multiple access with collision detection error 6–20 See also Frame check sequence See CSMA/CD CSMA/CD CBER 3–13 counters B–1 mapping 3–13 ROM enable bit 3–13 CBIO 3–9 access to 3–17 autoconfiguration 3–54 address 3–9 mapping 3–17 CBMA 3–10 CSR0 3–18 address 3–10...
  • Page 255 Descriptor list address registers General-purpose timer register See CSR3 and CSR4 See CSR11 Destination address bit 1 6–18 Device select timing 3–5 Half/Full-Duplex autonegotiation description 6–25 programmable burst length 3–20 Hash C routine Dribbling bit 4–7 6–20 example C–1 Heartbeat collision pulse fail 4–13 Host communication...
  • Page 256 Memory space access to 3–4 3–6 Jabber clock 3–63 Memory write and invalidate enable command Jabber timer 3–6 interval 3–64 purpose of 6–29 characteristics 6–2 Joint test action group error 4–7 See JTAG A–1 location 6–1 JTAG management 3–46 description A–1 port 6–1...
  • Page 257 status 3–5 DMA conditions 4–30 Parking 5–19 end of ring 4–8 error summary 4–5 Password protection first descriptor 4–6 See SecureON frame length 4–5 frame too long 4–6 interface functions 1–3 frame type 4–7 purpose 5–1 last descriptor 4–6 multicast frame 4–6 implementation 6–1...
  • Page 258 3–54 Subsystem ID register software 4–27 See SSID Revision number 3–7 8–6 Runt frame port selection D–2 size 6–20 System error enabling 3–5 receive path 1–4 Target disconnect SecureON termination 5–16 overview 8–1 Target retry Security data transaction 5–17 See SecureON TDES0 4–11 Serial port autosensing...
  • Page 259 start of list 3–25 Watchdog timer threshold 3–38 line status 3–29 Transmit descriptor 0 purpose of 6–29 See TDES0 receive 4–7 Transmit descriptor 1 receive disable 3–63 receive release 3–63 See TDES1 Write cycle Transmit descriptor 2 memory 5–9 See TDES2 slave 5–4 Transmit descriptor 3...

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